There are ever-increasing demands on complexity and production timelines for integrated circuits. This puts pressure on chip designers and design processes, and ultimately results in buggy designs with potentially exploitable mistakes. When computer chips underpin every part of modern life, enabling everything from your cell phone to your car, traffic lights to pacemakers, coffee machines to wireless headphones, then mistakes have significant consequences. This unfortunate combination of demand and increasing difficulty has resulted in shortages of qualified engineers, with some reports indicating that there are 67,000 jobs in the field yet unfilled.

In this tutorial we will explore what's coming next: EDA applications from the newest type of artificial intelligence, generative pre-trained transformers (GPTs), also known as Large Language Models. We will show how models like the popular ChatGPT can be applied to tasks such as writing HDL, and how LLMs of this nature can be leveraged alongside EDA tools to automate the process of creating functioning hardware using a process we have termed AutoChip.

Jason Blocklove is an Adjunct Ph.D. faculty member in the Electrical and Computer Engineering department at New York University. He previously worked at the Johns Hopkins University Applied Physics Lab where he worked on digital hardware and embedded system design. His research focuses on additive manufacturing security, leveraging generative AI models for hardware design, and security analysis of AI models for generating hardware.

With Moore’s law running out of steam, EDA tools now play a crucial role in meeting these computational demands. EDA tools are challenged to build chips that not only compensate for slow down in scaling, but also provide high performance for both ML and non-ML applications, which use a variety of new architectural techniques and operate under stringent performance constraints. Conventional EDA tools involve computationally expensive analysis and optimizations and are suboptimal as they often tradeoff speed for accuracy. ML promises to address these challenges as it has found tremendous success in solving these problems in classification, detection, and design space exploration problems in several different applications.

In this talk, I will show how leveraging ML techniques can revolutionize EDA tools by addressing the existing challenges. In particular, the talk will focus on tools that aid designers in (i) delivering power inside the chip without significant losses to meet power demands and (ii) sending the heat outside the chip to avoid high temperatures. The first section of the talk will show how a fast ML inference brings down several hours of runtime to a few milliseconds on industry-scale designs for these tasks. The second section will demonstrate how ML enables high-quality solutions through rapid optimizations. A key challenge with the proposed ML-based methods is the limited availability of open-source data and benchmarks for training and evaluation. The third section will show how ML can generate synthetic training sets and benchmarks for evaluating novel EDA solutions to these tasks. I will conclude by presenting avenues for future research in ML and EDA.  

IC design has a successful history of using automation to synthesize designs from Hardware Description Languages to realized silicon. PCB and package design have traditionally been completed through a painful manual process. Cadence’s new product for PCB place-and-route breaks this trend. Cadence’s X AI technology offers automation that augments the user’s design knowledge resulting in multiple alternative solutions in minutes, not days.

The key to this breakthrough is using AI where pertinent. The talk will discuss several classes of AI used. There will be a concentration on using a Convolutional Neural Net as a route goodness predictor that is the fitness function of Genetic Optimization system. These technologies are imbedded in a released product used by many of Cadence’s customers. All technology has successfully been patented over the last 4 years of development. The talk will focus on the messy, real world problems and how ML can be a proxy for the intractable problems of searching through a vast design space for multi-objective solutions.

Assured Large Language Model Software Engineering (Assured LLMSE) addresses the twin challenges:

1. Ensuring LLM-generated code does not regress the properties of the original code
2. Quantifying the improvement over the original archived by the improve code in a verifiable and measurable way.

In so doing, the Assured LLMSE approach tackles the problem of LLMs' tendency to hallucinate, as well as providing confidence that generated code improves an existing code base. This keynote outlines the overall approach to Assured LLMSE, and presents initial results.  This is joint work with Nadia Alshahwan, Andrea Aquino, Jubin Chheda, Anastasia Finegenova, Inna Harper, Mitya Lyubarskiy, Neil Maiden, Alexander Mols,  Shubho Sengupta, Rotem Tal, Alexandru Marginean, and Eddy Wang.

Alexander Suppes  holds the role of Consulting Engineer in the x-ray and CT business unit of Waygate technologies responsible for partnerships and evaluations of new technologies for the business. Before that, he was leading the software development team for x-ray and CT products. Alexander has joined the business 2003 and holds a PhD degree in Computer Vision from the University of Hannover, Germany.

Florian Knigge  joined Waygate in 2010 as a software engineer for x-ray and computed tomography. After several roles in technical sales, he moved to his current role as product manager for Waygate’s software offering in the radiography systems business. He holds a diploma and master’s degree in electrical engineering from the University of Applied Sciences and Arts in Hannover, Germany.

Ron Press is the senior director of technology enablement for the Tessent product family at Siemens Digital Industries Software. As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference (ITC) Steering Committee, and a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Ron holds patents on reduced-pin-count testing, glitch-free clock switching, and on 3D DFT.

Ron started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor's award for a system built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995. He joined the Mentor DFT organization in 1997.

Michael is an NI Fellow, focused on long-term innovation for Product Analytics at NI.  Additionally, he supports various other activities, including software strategy, sales, marketing, product planning and R&D.  He also evangelizes NI enterprise software solutions to customers, partners and industry forums.

Michael joined NI from OptimalPlus, which was acquired by NI in June 2020.  During his 15-year tenure at OptimalPlus, he served in several leadership roles including Chief Software Architect and CTO, designing, architecting and prototyping many of its flagship products as well as providing support for sales and marketing.  Most recently, he was the Corporate Technology Fellow in the business development team.

Previously, Michael was a Senior Software Architect at SAP, a Software Architect at Microsoft, and also held various managerial roles in software startups.