This talk will provide a better understanding of thermo-mechanical challenges and factors to maximize the performance of present and the next generation of silicon. In this talk, the audiences will be able to clearly see the full picture to answer the question of the different approaches of packaging interaction with the system from a thermo-mechanical point of view. Also, the talk will give a more complete understanding of the manufacture and assembly, materials behavior, the mechanical stresses, the end user application, and the target thermal performance. It is not a surprise to find taking the wrong direction can impact the package performance losing more than 30% to 50% of its performance.

Dr. Gamal Refai-Ahmed, Life Fellow ASME, Fellow EIC, Fellow IEEE, Fellow Canadian Academy of Engineering, is Xilinx Fellow a Chief Thermo-Mechanical Architect. He obtained the Ph. D. degre in Mechanical Engineering from the University of Waterloo.

He has been recognized as one of the global technical leaders of thermal management through his numerous publications (more than 100 publications) and patents& patents pending US (more than 50) and International (more than 120). His contributions are clearly seen in several generations of both GPU and FPGA products.

Gamal is the recipient of 2008 excellent thermal management award, 2010 Calvin Lecture and 2013 K16- Clock award in recognition for his scientific contributions and leadership of promoting best electronics packaging engineering practice. In 2014, Gamal received the IEEE Canada R. H. Tanner Industry Leadership for sustained leadership in product development and industrial innovation. In 2016, ASME awarded Gamal the ASME Service Award. State University of New York, Binghamton University awarded him the Innovation Partner Award for his industrial role with Binghamton University. In continuation to Dr Refai contributions to the best engineering practice, State University of New York at Binghamton awarded him the Presidential University medal in 2019 which is the highest recognition honor by the university. In 2020, Gamal was elected to both IEEE Fellow and EIC Fellow.

The quest to get more performance from microprocessors of Intel and rest of the industry alike has put immense pressure on manufacturing / test engineers. From gen-to-gen more cores are squeezed into the chips and the topmost frequency any individual core can run has been climbing steadily. At the lower side of frequencies, the number of cores which execute simultaneously at TDP and multicore workloads has gone from 4 to 10 in client space and 8 to 28 or 32 in the server segments. This increases raw power consumed and the heat to be removed. On the other end single or dual core turbo frequencies are hovering around 5-5.5GHz with very high voltages, increasing the both leakage and dynamic power in a non-linear fashion. As the industry moves to smaller nodes more transistors are crammed into smaller area. Now it is no longer a raw total power problem. The villain here is power density. Though system thermal engineers have their fair share problems to talking power and thermal density the challenges to the test and manufacturing engineers cannot be understated. In this presentation we will see some historical trends of physical aspects of the microprocess / cores to highlight the impending problem of being “too hot to test”. Next some challenges unique to test / manufacturing environment are discussed. Bare die and Lidded parts are contrasted; Server and client products are compared for their own set of problems. Different types of tests content viz Scan / ATPG, Cache load / full width functional tests and Cache BIST tests are deliberated w.r.t to the amount and density of power consumed and potential loss of frequency and binsplit due to lack of effective thermal control. Difficulties in telemetry to measure the real Tj of the silicon as well as problems in thermal control equipment to react to fast changing / transient nature power consumption during test with an Illustration with one of the recent 14nm core products data is presented. Finally, possible approaches to mitigate this “too hot to test” is put forward: Designing the cores/CPU to move the hotspot, spreading out the power / flattening the power density curve, designing the test , DFx methods for low power consumption, finer granular spatial temperature telemetry and fast thermal control for bare die and lidded products, new TIM materials, machine learning, data analysis.

Arun Krishnamoorthy, a Senior Principal Engineer, joined Intel in 1999 as a Product Development Engineer and started to work on the first Intel P4 processor on thermal and power issues. Over the next 20 years he has worked on the entire line of client processors and few of the server processors. Arun has developed several test methods for HVM as well as device validation for variety of IPs like Digital Thermal Sensors, Power Control Unit, Fully Integrated Voltage Regulators as wells test algorithms for power and speed binning. Arun holds 5 patterns, and has authored several internal papers / journal articles in the field of test / system thermal management. Arun has a MSEE degree from UARK with a focus on High density Electronic Packaging and Thermal aspects of microelectronics.

Temperature is an important indicator to the health of device, but could it be used as metadata in test execution to optimize yield or COT? In many cases, the time required to run IC tests, particularly scan (structural) tests, is limited by the resulting temperature of the device during this special test case where a large number of transistors are being toggled simultaneously. This presentation will discuss trends in scan architectures that promise to help solve this problem, as well as device characterization techniques that can help to optimize scan speeds and test flows to get the fastest test time given the thermal limits.

Ken Lanier has been in the ATE industry for over 30 years. He has held positions in applications engineering, system instrument design, as well as engineering and marketing management. He is currently a Principal Technologist in the SOC test division at Teradyne in North Reading, Massachusetts. He was formerly a Director of Marketing at LTX. He received his Bachelor’s degree in Electrical Engineering from Worcester Polytechnic Institute.

For many years, the Advantest team has worked hard to provide an IC test environment which is both safe and effective for testing the highest power devices in the industry. Along the way we have developed many test methods which are most effective for testing this special breed of device.

This paper will discuss some best practices which we have learned along our journey.

• Effective power delivery and voltage sensing techniques.
• Managing power sequencing.
• The importance of a carefully engineered Power Distribution Network.
• Active Thermal Control signals.
• Techniques to minimize the possibility of probe burn

In summary, this paper will point to some of the fundamental constraints which limit what testing is achievable in this situation.

In his capacity as Director of Business Development, Dave Armstrong works directly with customers and Advantest’s global R&D teams to define develop and deliver creative solutions to the most demanding test challenges. Additionally, Dave is currently the Chairman of the Test focused working group of the Heterogeneous Integration Roadmap.

Prior to joining Advantest in 2004, Dave spent over two decades in HP/Agilent’s IC test group achieving the role of Principal Engineer. Prior to joining HP Dave worked in the semiconductor industry in areas of IC and system design, product/yield engineering, as well as test engineering. Dave Armstrong received degrees in Electrical, Computer, and Environmental Engineering from the University of Michigan in 1974.

Today’s EDA tools have integrated and creative facilities to analyze and mitigate power use at test application time. These features encompass both the DFT synthesis capabilities and test pattern generation components, as well as in-system measurement capabilities for calibration and correlation routines. Recent tool automation has integrated mainstream power analysis tools with pattern generation to guide the tools to prepare patterns that don’t break the budget. But the feature set is wide and deep. Some features mitigate shift power; with some tailored to the specific DFT architecture being addressed. Other features mitigate capture power. Some features apply to the hardware. Others apply to the pattern generation step. In addition, process, voltage, and temperature monitor insertion and integration with powerful analysis capabilities have presented designers with the tools needed to correlate pre-tape-out analysis with in-system measurement. This presentation will list power reduction features (some available in many EDA tools) and explain the correlation efforts with silicon models and in-system measurement results.

Adam Cron is a Principal Engineer at Synopsys working with customers worldwide on complex DFT and ATPG issues for digital ICs. He is part of the Hardware Analytics and Test R&D group, and has been with Synopsys for over 23 years. A Syracuse University graduate, Adam also worked in test-related fields at Motorola and Texas Instruments for over 36 years in the industry. Adam is Chair of IEEE Std 1838 which standardized 3D-IC test access, and chaired the IEEE Std 1149.4 Working Group through its release. He is a member of, or has worked with, various IEEE standards’ efforts including 1149.1, 1500, 1687, etc. Adam is also the outgoing Chair of the Test Technology Technical Council's Test Technology Standards Committee which oversees the development of Test standards, and is an IEEE Golden Core recipient. He has authored various papers and book chapters through the years, and is frequently a moderator, panelist, or invited speaker at various test-focused conferences.

This presentation will focus on using System Level Power models, such as IEEE2416, for power modeling. System Level power models allow the whole system to be modeled and model transparently updated with the latest data. System Level power enables System Under Test power models to be easily created resulting in exploration of different test scenarios.

A proposed flow for early power analysis will be shared with the audience.

The talk will also highlight how test conditions, such as differences between user and test system setup, voltages, temperatures, affect power analysis and need more robust handling.

We will highlight some of the features of our EDA software, PowerMeter, specifically targeting System Level power analysis, and how the tool was applied on chiplet system to estimate system power.

David Ratchkov is the Founder and CEO of Thrace Systems, a EDA company on a mission to reduce power dissipation in semiconductor devices through better tool, modeling, analysis and simulation. David started his career in the semiconductor industry in the distant 1999 at what was then LSI Logic and has spent most of his time working on power related tools and methodologies.

David holds MS in Mathematics and Computer science from University of Plovdiv, Bulgaria.

Areas within electronics thermal management that are receiving a very high level of focus for performance improvement and development include:

Advanced thermal materials

• High-performance thermal interface materials for very high heat flux conditions
• Thermal interface materials for semiconductor test
• CTE-matched thermal materials
• High thermal conductivity heat spreaders
• Solutions for device deformation under thermal stress

Advanced thermal control solutions applicable at the package level

• Heat pipe, vapor chamber, and thermosyphons
• Fast-responding thermal control solutions including two-phase technologies

An understanding of thermal material categories and the relative uses and functions of each is particularly important, as thermal management increasingly has focused on minimizing the sources of greatest thermal challenge in package structure and integration into systems.

Dave Saums founded DS&A LLC as an independent consulting firm in 2003, assisting firms in assessing electronic thermal management markets and systems requirements for new business strategy, new product development concepts, and new product testing and introduction. Prior to this fifteen year period as an independent consultant, Dave worked for four different thermal management component, systems, and materials manufacturers over a twenty-five year period. This included managing a product development engineering team, managing development of a new manufacturing business with tens of millions of heat sink assemblies shipped per month, with evaluation of TIMs for those assemblies.

Work experience also included business development for CTE-matched thermal materials, work on the first phase-change TIMs, mil-grade airmovers, and two-phase liquid cooling systems, with hundreds of visits to engineering groups globally in power electronics, telcom, computing, and semiconductor manufacturing companies. He has been the general chair for an advanced technology workshop on thermal management for twenty-one years in the US, has served as co-chair for four power electronics thermal management workshops in the EU, participated in sixteen years of organizing and presenting for an IMAPS France thermal workshop, and proposed and chaired a new power electronics thermal workshop that was held very successfully with Semi-therm and Binghamton University (NY) in July 2020.

Dave earned BS and MBA degrees from Clarkson University, was named Society Fellow for IMAPS in 2010, and is a member of IEEE and SAE.

The AI, Automotive and 5G markets continue to grow at a very rapid pace and an increasing number of chips with high power consumption are being designed and manufactured for those applications. This creates a major challenge for test vendors to provide advanced probe cards that can house a large number of probes while at the same time effectively manage the thermal load during testing due to high current and high temperature environment. The presentation will introduce a new, customizable MEMS probe-based hybrid style probe card, developed to meet the demanding test conditions of these high power consumption devices.

The hybrid probing solution begins with a flexible MEMS Probe and an optimized proprietary probe head. The presentation will cover the overall design of the probe head - mechanical and electrical parameters (stack-up material, fixed pitch and current requirement), and the customization of the MEMS probe. The probe head is built with a mix of differing probe diameters and allows for a combination of high current and non-high current probes in order to simultaneously handle the high current with lower power consumption. With the flexibility of the MEMS probe, both probe types utilized in the probe head will still maintain the same probe force, stroke & probe length, making it possible to even probe various height pads with the same probe card.

This paper will also discuss briefly the application of the same hybrid technology for high-speed applications by establishing a transparent transition between the PCB and wafer via impedance matching.

Karan Maniar is a Mechanical Engineer with Nidec SV TCL in Tempe, Arizona. Karan is responsible for working with the Nidec SV TCL Engineering Team on various product development and capability enhancement projects. He has experience with a several design and simulation software platforms and analytical equipment. He is a graduate of Mumbai University, India and Arizona State University holding both a Bachelor of Science and a Masters Degree in Mechanical Engineering.

The key challenge is that for AI chips, as well as the trend of increasing DPW for memory chip, are driving the heat generation inside the test cell. As a result, when the wafer test chuck temperature is intended for room temperature, the device understand can be as hot as over 100C when powered up for testing. In addition, this is making cold test nearly impossible. Our solution is to implement adaptive thermal management capability for customers to actually test the device at the intended temperature.

Jerry Tustaniwskyj is currently the Director of Technology Development at Cohu, Inc. and also is a part time faculty member at the University of California, San Diego Mechanical and Aerospace Engineering department. A major responsibility he has at Cohu is the development of the thermal control architecture used in the test handlers that they produce. He received a B.S. and a Ph.D. in Mechanical Engineering from Wayne State University. Jerry has a total of 48 years’ experience in the electronics industry, working on computer peripherals, mechanism design, device packaging, and thermal control. During that time, he has been awarded 53 patents with 4 pending.

The connected microelectronics devices cover a broad spectrum of form factors, packaging architecture and power consumption. The packaging technology has evolved since organic flip chip packaging in the 1990s. In the last decade, the innovation in packaging has shifted to heterogeneous on-package integration (2.5D and 3D) with the major driving factors being Si process scaling, interconnect scaling, the need to integrate IPs with difference functions, yield resilience and time to market. The new advanced packaging technology brings challenges in thermal management by increasing power and power density, increasing package thermal resistance in 3D stacking and thermal crosstalk. Different Tj requirement for each functional IC and thermo-mechanical enabling for large form factor packages with multiple chips bring additional challenges for cooling solutions. A cost-effective cooling solution needs to provide a holistic approach which consists of thermally aware design (heat source), component and package thermal improvement, and cooling solutions and system design. The thermal community has recognized these thermal challenges and the needs for innovation in thermal management. Starting 2018, a group of thermal experts from academia and industry have been collaborating in thermal technical working group (TWG), a subchapter of Heterogeneous Integration Roadmap (HIR), to identify key technical challenges and potential solutions. This presentation will summarize the progress this thermal TWG has made.

Weihua Tang manages a Research and Development engineering team that specializes in thermal and fluids competency with a focus on package thermal technologies, thermal modeling methodology, and fundamental understanding of semiconductor substrate packaging, assembly, and test process covering a broad range of product segments. She has 10+ years of experience in semiconductor industry. She is an associate editor of IEEE Transactions on Components, Packaging and Manufacturing Technology and a contributor to IEEE HIR Thermal Technical Working Group.

This presentation describes the thermal management and operations challenges of testing packaged integrated circuits (ICs) and microelectromechanical systems (MEMS) devices. Its focus is on device thermal conditioning to simulate the extreme conditions in which the devices will operate, and some of the existing solutions introduced for volume production will also be provided. A growing portfolio of integrated circuits that present significant challenges are high-power devices – generally designated as devices that operate with minimum 100W and have roadmaps to +500W. The presentation will address this class of devices and their special test requirements.

Today’s integrated circuits take advantage of a variety of packaging technologies. During manufacturing, each IC device must be electrically tested at elevated and depressed temperatures (typically -55°C to 160°C) before shipment to properly sort them by performance (i.e., clock speed). This final testing also determines general characteristics, such as whether a device is defective or meets minimal functional performance specifications, primarily for automotive products.

As a provider of turnkey manufacturing processes and premiere automotive devices, Amkor continues to face challenges related to large production volumes and optimized operation costs necessary to provide IC devices economically and profitably. The challenges that need to be addressed are outlined below, but not limited to:

• Achieve temperature accuracy within ±2oC
• Minimize temperature stabilization time
• Reduce the maintenance and change over time
• Utilize a small footprint chiller
• Minimize facility requirements
• Achieve high parallelism with uniform temperature
• Accomplish rapid temperature cycles

Considering the large variety of packages and given the trend towards more stringent requirements, there is no one solution that can be generally used. Instead, Amkor has an aggressive roadmap for evaluating and implementing creative best-in-class solutions, either developed internally or by partnering with established suppliers. Techniques to be detailed in the presentation will address some of these challenges, including solutions for:

• Automatic test controller and chiller with no liquid nitrogen (LN2)
• Chamber-less cold testing
• MEMS multi-sites environmental testing
• Small footprint environmental testing for large parallelism memory products
• Tri-temperature testing in one insertion

Andrei Berar joined Amkor in 2018 and is Sr. Director Test Business Development, WW Test Services. Prior to joining Amkor, Andrei worked at KYEC USA for 7 years as Executive Director Sales Marketing, with responsibility for test services business development in North America. He holds a MSME degree from the Polytechnic Institute, Romania and an MBA from Pepperdine University.

Advances in high-end floating-point processing, machine learning, and Artificial Intelligence have led to a new class of devices that demand performance at all power costs. As a result, extremely high-gate count devices are being designed that have incredibly high power draws – it is not atypical to see chips requiring 350W to 650W today. The requirements of this market are expanding aggressively. Leading companies are forecasting multi-billion transistor IC designs that will require >800W of power dissipation in a single FC-BGA package

As such, the traditional heatsink with fins and fans are no longer sufficient. Currently, IC cooling during manual test is achieved by using cold plate (close-loop liquid cooling), heatpipe or vapor chamber and cold plate with chiller, etc…

• Cold plate (close-loop liquid cooling) can dissipate up to 350W. This liquid cooled heatsink is connected to the water supply available in the lab facility.
• Heatpipe or vapor chamber can dissipate up to 500W. Heatpipe and Vapor chamber require lot of volume and adequate air flow.
• Cold plate connects to a portable chiller which uses refrigerant and vapor compress can dissipate 900W and above.
• Thermoelectric cooling which takes advantage of the Peltier effect.
• Thermal Bath with non-conductive engineering fluid.
• Thermal Control Unit with the capability for direct temperature feedback.
• Thermal Interface Material (TIM): low thermal resistance, highly compliant, re-useable with repeatable performance

This presentation will discuss the advantages and disadvantages of the available cooling solutions. As IC power is forecast to approach 1000W in the near future, keeping IC cool during test must be considered in advance, ideally during initial stage of the IC design and System integration levels.

Quynh Nguyen is a Mechanical Engineer at Smiths Interconnect America, located in Milpitas, California since 2014. She holds a B.S degree in Mechanical Engineer from San Jose State University, major in Mechanical Design and minor in Thermal. She has more than 15 years of mechanical design and thermal management experience in the Semiconductor Test Industry.

Tim Wooden is a Product Line Manager at Smiths Interconnect America located in Milpitas, California. He an expert in semiconductor package test, with deep experience in the design, deployment, and application of advanced test socket solutions, System Level, RF Testing, PoP, SoC, High Power, Thermal and Fine Pitch. With specific expertise in Technical Sales, Product Development, Marketing and Business Development, Tim has worked for Smiths Interconnect for almost two years

The key challenge is that for AI chips, as well as the trend of increasing DPW for memory chip, are driving the heat generation inside the test cell. As a result, when the wafer test chuck temperature is intended for room temperature, the device understand can be as hot as over 100C when powered up for testing. In addition, this is making cold test nearly impossible. Our solution is to implement adaptive thermal management capability for customers to actually test the device at the intended temperature.