Bapi Vinnakota currently leads the Open Domain-Specific Architecture sub-project, within the Open Compute Project. The ODSA has active volunteers from over 50 companies and has 8 active
workstreams with several activities essential for establishing an open Chiplet economy. Achievements by ODSA include  the release of the Bunch of Wires (BoW) die-to-die Interface (now in products at multiple companies) and CDXML, the first open spec for the physical description of chiplets

Jawad Nasrullah serves as CEO of Palo Alto Electron, a heterogeneous integration company focused on chiplets and 3D-ICs for hyperscale computing. He was previously President, CTO, and Co-Founder of ZGlue, the creator of a platform for developing chiplets as well as a marketplace for distributing them. Before co-founding ZGlue, he was an engineer at Samsung Electronics, Intel, and Sun Microsystems. He earned a Ph.D. in EE at Stanford, has 6 publications, and holds 14 patents.

Richard (Dick) F. Otte, has been President & CEO of Promex Industries Inc. since 1995.  Promex is an ISO 9001:2015, ISO  13485:2016, and ITAR-registered manufacturing services company that specializes in the onshore mixed technology assembly of medical, biotech, and semiconductor devices in its facilities in Santa Clara and Escondido, California (DBA QP Technologies).

Before that, he was the General Manager of AMP’s Kaptron Optical Products Subsidiary and President of Advanced Packaging Systems, a Raychem-Corning Joint Venture.  Earlier in his career, Mr. Otte was an electronic engineer and Program Manager.

Otte is a member of the IEEE, IPC, Optica, SMTA and the MIT Communication Technology Roadmap Advisory Board, Over 75 patents issued throughout the world list him as an inventor. 

He has a BSEE, an MSEE from MIT, and an MBA from Harvard University.

David Ratchkov is the CEO of Thrace Systems, a provider of Electronic Design Automation (EDA) tools with a focus on tools and flows for the system integration of 2.5D/3D Integrated Circuits (ICs). He also co-leads the CDX (Chiplet Design Exchange) workstream under the Open Compute Project’s Open Domain Specific Architecture sub-project. Previously he worked at Broadcom (Avago, LSI, LSI Logic) in various EDA roles, spanning physical design, power analysis, and modeling. He holds an MS in Mathematics with a specialization in CS from the University of Plovdiv, Bulgaria, and has 9 issued patents.

Michael Herndon is the Director of Research and Development at Epirus Inc. which focuses on defense and advanced electronic solutions. Before joining Epirus, he spent over 20 years at Northrop Grumman space sector developing Antenna systems, electronically scanned phased array systems, and advanced receiver architectures. He served as the Chief Technologist at Northrop Grumman for a critical mission segment for the warfighter overseeing a diverse set of programs ranging from space vehicles, microelectronics, digital and artificial Intelligence, and others.

Dr. Islam (Sam) Salama is a technology and business executive with 2 decades of experience in the semiconductor industry.  He is currently the chief executive at Hyperion Technologies- a U.S.-based microelectronic systems manufacturer. Before Hyperion Dr. Salama was a Vice President, and General Manager with Intel Corporation, overseeing manufacturing, operation, and supply chain for packaging and high-density interconnect substrates- a $3.5B annual business. His organization led a network of 18 global high-volume manufacturing factories producing more than 1B units annually across intel and its foundry products. His supply chain division managed business operations across an expansive ecosystem (including more than 10 global hybrid manufacturing subcontractors and 100+ equipment and materials OEMs). Dr. Salama is leading the team to position Hyperion at the forefront of business operations and technology leadership to establish a U.S.-based, independent merchant provider of system-level 3DHI solutions including a trusted and assured advanced packaging foundry.  Before his General Manager role with Intel, Dr Salama was the Senior Director of Technology Pathfinding for Intel assembly test TD organization. In this capacity, he managed a team of technologists, architects, and process engineers focusing on system architecture, process development, next-gen materials, substrate, and assembly technologies. Dr. Salama is a board member at several microsystems, photonics, and advanced manufacturing companies. He is an elected fellow and board of trustees member with the Laser Institute of America. He has authored more than 130 patents in a range of areas, including device fabrication, high-density interconnect technologies, microelectronics packaging, product architecture, system-level design, laser materials processing, and materials engineering. He has published more than 30 technical articles, book chapters, and industry reviews in similar fields of expertise. Sam is passionate about mentoring youth and promoting education, economic awareness, social justice, and prosperity through manufacturing.

In the ever-evolving landscape of the semiconductor industry, the deceleration of Moore's Law and the continuous progression of silicon technology nodes present challenges that demand innovative solutions. Emerging as a formidable catalyst for transformation, packaging technology has transcended the confines of traditional silicon-centric advancements. This paradigm shift is exemplified by chiplets, where diverse architectures and technology nodes converge seamlessly, unlocking a host of opportunities.

Beyond the significant enhancement of GPU performance, chiplets usher in a new era of design flexibility, allowing engineers to repurpose their creations across a broad spectrum of products. As we navigate this dynamic terrain of chiplet technology, the evolution of 2.5D and 3D interconnect innovations takes center stage, driving industry-wide objectives.

Among these innovations, Wafer-Level Fan-Out (WLFO) technology assumes a prominent role. Its cost-effectiveness and utilization of organic materials make it a linchpin in semiconductor packaging. WLFO facilitates the attachment of chiplet interconnect modules to a substrate through a monolithic flip-chip assembly process, further enhancing the versatility of chiplet integration.

A crowning achievement in this journey involves AMD's pioneering efforts, leading to the development of groundbreaking 4L WLFO products for Radeon Technology Graphics of Navi3x. This accomplishment is poised to reshape prevailing industry benchmarks and establish fresh paradigms for innovation.

In our upcoming presentation, we will explore the intricacies of these technologies, shedding light on their multifaceted advantages. Additionally, we will share our ongoing efforts to refine and optimize these solutions for high-volume production (HVM) and improved yield, thereby solidifying their pivotal role within the ever-evolving semiconductor landscape.

This is the accordion body content. It is typically best to keep this area short and to the point so it isn't too overwhelming.

Chiplets or die partitioning offers a compelling value proposition for yield improvement, IP reuse, performance and cost optimization. Advanced packaging technologies such as 2.5D Si TSV interposer, Fanout RDL interposer and 3D hybrid bonding packaging have been developed for chiplets and system heterogeneous integrations to fulfil the continuous pursuit of higher performance, higher bandwidth and lower power consumption at a more manageable cost. However, the chipletsintegration solutions especially for HPC, Networking, AI and Edge computing applications have also urged the demands for advanced packages with higher density interconnects and larger footprint body sizes. The package layout density can reach tens or even hundreds of times than that of conventional FCBGA packages. How to optimize the layout to get the optimal performance among the chiplets has become very critical. High density and complex connectivity in advanced packaging cause more difficulties and challenges by using traditional EDA tool for packaging design and assembly manufacturing validation. Moreover, the die to die interconnects for chiplets integration are usually proprietary links from different customers, thus also create more design boundaries and limits the adoption of advanced packaging technology.

In this presentation, a new design flow and platform for advanced high density package technology were introduced. The design platform was used to complete the routings of ultra-high density I/O such as the Si interposer MEOL (Middle End of Line) and Fan-Out RDL interposer. Compared with the traditional design platform, it had reduced the design cycle time and improved the design accuracy. Moreover, this new design platform is also used to leverage and validate open standard Die to Die interconnects through UCIe (Universal Chiplets Interconnect Express) open ecosystem. Furthermore, a new PDK (packaging design kit) has been established to provide the design rule checking (DRC and LVS) and procedure to the IC or system designers. Finally, from OSATs perspective, the design challenges and collaboration with system and IC design companies on chiplets integration were also elaborated.

 Dr. Lihong Cao is a Sr. Director in ASE Group responsible for advanced packaging technology development, new product introduction, and business engagement. Her expertise spans from design, process development and production enablement. She leads chiplets Die to Die interconnect standardization effort in UCIe (Universal Chiplets Interconnect Express) consortium as Board of Director of ASE 

     Prior to joining ASE, as a senior manager, Lihong led advanced packaging technology qualification worldwide in AMD for 16 years. She also had academic experience as a Research Associate Professor in Nanyang Technology University in Singapore.

Ayar Labs

Lakshmikant (LK) Bhupathi

Vice President of Products, Strategy and Ecosystem

LK joins Ayar Labs following twenty years with Marvell Semiconductor in a variety of design, technical marketing, and product roles, including a position as Vice President, Product Management / Marketing at high performance networking company Aquantia (acquired by Marvell), as well as driving CXL and Ethernet NIC product strategy and roadmap for Marvell’s next-generation cloud and enterprise datacenter applications. LK also served as the President and Marketing Chair for the NBASE-T alliance (since merged with the Ethernet Alliance). He holds an MBA from the University of California, Berkeley.

Over the last years, a trend has emerged to build large and complex digital devices like high-
end MPUs, GPUs or AI accelerators as an array of individual dice mounted side-by-side on a

carrier (2.5D) or on top of each other (3D) in one common package. Interconnection between
the dice is made by established standards like JEDEC HBM for logic-to-memory, or the new
Universal Chiplet Interconnect Express (UCIe) standard for logic-to-logic. These short-reach,
high-bandwidth die-to-die interfaces provide extremely high bandwidth at very low power, but
they come with extra challenges for testability in production.
The standards are meant for very high-bandwidth, short-reach connections between chiplets –
few mm on a carrier for 2.5D and through-silicon VIAs (TSVs) for 3D integration, depending on
the package. Signals are packed with very high density per mm, and electrical specifications are
optimized for short reach and low power consumption, as the path to the neighbor chiplet is very
short. To pack as many signals as possible in a small area, the pitch is very dense and micro
bumps are used for the connection. The combination of these two characteristics typically
prevents any direct external test access of the specific interface during wafer test using
automated test equipment (ATE).
While custom approaches are being used selectively for die access in wafer test today, several
industry players have expressed their interest in a standardized solution for high bandwidth ATE
access to UCIe-enabled chiplets both on wafer and in package. In this paper, we will describe
some of the challenges and discuss various approaches as basis for further discussions.