Heterogeneous Integration opens an exciting world of possibilities for semiconductor products. There is the promise of product differentiation and the allure of flexibility. Included in this is a mix-and-match product architecture approach that provides immunity to the challenges of Moore’s law and the flexibility to include late-binding product features. These benefits do not come without a price, the challenge is that the interactions between the package architecture and chip complex become increasingly complex and intertwined. If this complexity is not addressed upfront during both die floor planning and package planning and design, the resulting incompatibilities can undo the advantages promised by heterogeneous integration. This talk focuses on the challenges of planning, development and design for effective integration of advanced packaging technologies with heterogeneous die architectures to create high-performing, differentiated, best-in-class products. The role of tools and flows in enabling effective planning and design in an integrated approach, rather than siloed, for both die and package planning will be detailed.

Sujit Sharan received his bachelor's degree in Materials Science from IIT Kanpur, India and a Ph.D. in Materials Science and Engineering from NCSU, Raleigh, NC in 1990. He has over 30 years of experience in semiconductor processing and packaging areas working for Hampshire Instruments, Micron Technology, and Intel. He joined Intel Corporation in 2000 where he is currently a Sr. Director of the Advanced Design and Technology Solutions department within Assembly and Test Technology Development. Sujit has vast experience in the semiconductor industry having worked in multiple areas, including x-tray lithography, CMP and advanced thin film processing. Before joining Intel, he worked for Micron Technology developing new interconnect technologies for DRAM and Flash memory. Currently, he is working on developing and driving the lowest total product cost through package design optimization and innovative package architecture solutions. He has over 180 issued patents and over 30 published papers in academic and refereed journals and has given multiple invited talks at various conferences.

Whether you are an ASIC designer or package designer, you can expect several new design and analysis challenges when transitioning from the world of single die architectures to the world of More-than-Moore. 3D integration of these multi-chiplet designs raises even more challenges. This presentation will outline the trends and design challenges related to 3D-IC architectures.

John Park brings over 35 years of design and EDA experience to his role as Product Management Group Director for Advanced Semiconductor Packaging at Cadence Design Systems. In this role, John leads a team responsible for defining cross-domain solutions and methodologies for IC, package & PCB co-design and analysis. Over the past three years, John has authored numerous publications on emerging trends in multi-chip(let) package design and analysis.

When it comes to the question of whether to build a design using chiplets, there are many factors to consider, such as industry standards (or lack thereof), availability of chiplets within the supply chain, size requirements, and cost. The cost of chiplets is a particularly important component that must be understood, because even if all design requirements can be met by the current chiplet supply chain, the chiplet package will not come to fruition if the total cost is too high. The basic tradeoff between a monolithic die and a series of chiplets is a reduction in die costs countered by an increase in packaging costs.

This presentation will analyze three advanced packaging technologies suitable for chiplets: an interposer-based process, a chip-last fan-out process, and a fan-out process that relies on embedded pieces of silicon to form interconnect bridges. For all three processes, the package, whether interposer or fan-out based, is placed on a substrate before it is ready for PCB assembly. (This contrasts with simpler fan-out processes, in which a die is packaged in mold, redistribution layers are created, and solder balls are attached directly to the fan-out package before it goes on to PCB assembly.)

In addition to breaking down the cost components of all three selected technologies, the cost of packaging an example design as a monolithic die and in various chiplet-based scenarios will be analyzed. Not only will the costs of the packaging processes be considered, but the cost of the incoming die, chiplets, and yield loss will be included as well.

Amy is currently Vice President of Business Development at SavanSys, where she does cost modeling and analysis for companies in the electronics packaging and aerospace industries. Prior to joining SavanSys, Amy held positions in business development at TOK America and in engineering at Nokia Japan. In 2006, she received a Fulbright grant to study the cost impact of shifting to lead-free manufacturing, and her degree is in Chemistry. She has published numerous technical papers, been an invited speaker at conferences and seminars, and contributed to industry publications.

Marc Swinnen is Product Marketing Director for semiconductor products at Ansys in San Jose, CA. Before joining Ansys, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys, Azuro, and Sequence Design, where he gained experience with a wide array of digital and analog design tools. Marc holds a Master’s in Electrical Engineering and a Master’s in Industrial Management from KU Leuven, Belgium and an MBA from San Jose State University, California.

Kenneth Larsen is a product marketing director in the Silicon Realization Group at Synopsys. He is a versatile leader with a strong background in defining and executing product vision, marketing strategy, inspiring product development teams, translating technology concepts into customer solutions, developing high-performance global organizations, conceiving and driving new and emerging products to scale from the ground up, guiding marketing, and enabling sales. Kenneth has a degree in electrical engineering and additional coursework in strategic growth at Columbia Business School, and Artificial Intelligence at MIT Sloan School of Management.

With so many features of interest at play in computing, adding all the features of interest in the most advanced silicon process node to meet the ever growing computing demand is very challenging. Chiplet implementation uses a selection of modular dies, referred to as chiplets, to provide a heterogeneous integration approach and to offer best-in-class feature combination. However, identifying the key system design factors to enable a successful system is complicated.

In this report, a design factor sensitivity methodology will be presented. Chiplet system channel jitter is used as the desired optimized result and the impacts of different design factors on the result are examined.

Based on a behavior jitter model, this method first correlates the model to an actual measurement of a High Bandwidth Memory (HBM) system.

The model is then extended to represent different input factors for the system output data path jitter. These input factors include the multiple supply power frequencies, their corresponding noise amplitudes, signal transition slew rate, as well as channel routing configurations such as different ground signal configurations. A set of output jitter response surface model, with different power tone frequencies and noise amplitudes, is then developed, with an optimal channel interconnect. The response surface model provides a contour to identify critical input parameters such that system platform designers can evaluate the effects of multiple input factor and their interactions. This approach allows for a holistic consideration for optimizations & specification.

Thomas is with AMD focusing on System Memory Platform Architecture Development. Prior to AMD’s acquisition of Xilinx, Thomas was a Distinguished Engineer in System Memory Signal Integrity group. Before joining Xilinx, Thomas was with NVIDIA Advanced Technology Group focused on highspeed circuits & system channel designs. Before NVIDIA, Thomas worked for Intel for more than 16 years covered and led many different types of system memory IO development. Thomas received his PhD degree in Electrical Engineering from the Ohio State University in 1995 & he is the inventor of over 38 patents in the fields of mixed signal IO circuits and system memory configurations as well as high speed clocking for highspeed memory designs.

Ayar Labs is disrupting the traditional performance, cost, and efficiency curves of the semiconductor and computing industries by delivering up to a 1000x improvement in interconnect bandwidth density at one-tenth the power. We use standard CMOS processing to develop high-speed, high-density, low-power optical interconnect chiplets (i.e., monolithic electro-optical) and lasers to replace traditional electrical I/O with huge performance advancements. This talk will focus on Design for Manufacturability (DfM) coupled with the chiplet development and our Assembly & Packaging Test Vehicle for enhanced package manufacturability and reliability.

Steve Groothuis has a Masters in Physics (The University of Texas at Dallas) and a Bachelors in Physics (Michigan State University). He has worked for semiconductor companies (Texas Instruments, Micron Technology, and Intel Corporation), assembly & packaging companies (Samtec Microelectronics and Plexus Worldwide), simulation software company (ANSYS, Incorporated), and silicon photonics startup (Ayar Labs, Incorporated). At Ayar Labs, Steve is responsible for government program management and technology strategy and pathfinding activities.

Chiplets or die partitioning offers a compelling value proposition for yield improvement, IP reuse, performance and cost optimization. Advanced packaging technologies such as 2.5D Si TSV interposer, Fanout RDL interposer and 3D hybrid bonding packaging have been developed for chiplets and system heterogeneous integrations to fulfil the continuous pursuit of higher performance, higher bandwidth and lower power consumption at a more manageable cost. However, the chiplets integration solutions especially for HPC, Networking, AI and Edge computing applications have also urged the demands for advanced packages with higher density interconnects and larger footprint body sizes. The package layout density can reach tens or even hundreds of times than that of conventional FCBGA packages. High density and complex connectivity in advanced packaging cause more difficulties and challenges by using traditional EDA tool for packaging design and assembly manufacturing validation.

In this presentation, a new design flow and platform for advanced high density package design were introduced. The design platform was used to complete the routings of ultra-high density I/O such as the Si interposer MEOL (Middle End of Line) and Fan-Out RDL interposer. Compared with the traditional design platform, it had reduced the design cycle time and improved the design accuracy. In addition, this presentation also introduced Assembly Design Kit (ADK) to provide the new design rule checking (DRC and LVS) and procedure to the IC or system designers. It also demonstrated how DRC tools playing an important role in RDL process improvement. Finally, from OSATs perspective, the design challenges and collaboration with system and IC design companies on chiplets integration were also elaborated.

Lihong Cao is a Director in ASE Group responsible for new packaging technology development (2.5D/3D, FOWLP, FOCoS, PoP, SIP, SESUB), technology promotion, new product introduction, technical program management, strategic planning, and business engagement. Her focusing spans from design, process development & qualification, as well production enablement especially in HPC (High Performance Computing) and AI/MI (Artificial & Machine Intelligence)

The advent of smart devices, artificial intelligence and 5G is driving an explosion in demand for high performance computing (HPC). With the slowdown in Moore’s law, chiplet architecture is critical to sustain the rapid growth in HPC. In this talk, we will discuss the critical role of substrates and the need for design co-optimization at every stage of the product life cycle. We introduce machine learning based tools that are trained to estimate the impact of design on yield, cost, and capacity. We conclude with the benefits of these analytics tools and road ahead for advanced packaging.

Deepak Kulkarni is a Fellow, Advanced Packaging at AMD. Deepak has over 15 years of experience in packaging technology development. Over the years, he has held several leadership positions driving substrate technology development and yield improvement. Prior to joining AMD, Deepak was Senior Director of packaging yield at Intel Corporation. He holds eight patents and nineteen publications on various aspects of packaging such as 2.5D/3D architectures, DFM/DFY and AI techniques applied to yield management. His contributions to the semiconductor industry have been recognized by an Intel Achievement Award, Next 5% award (AMD) and best paper award (ITHERM). Deepak holds a PhD from the University of Illinois Urbana-Champaign with a major in mechanical engineering and a minor in computational science.

Dr. Debendra Das Sharma is an Intel Senior Fellow in the Data Platforms and Artificial Intelligence Group and Chief Architect of the I/O Technology and Standards at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. 

Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Technical Task Force. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.

Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst.​ He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the 2021 IEEE Region 6 Outstanding Engineer Award, and the 2022 IEEE Circuits and Systems Industrial Pioneer Award.