April 4 - 6, 2023
8-11 am Pacific
Today advanced semiconductor packaging is already delivering Heterogeneous Integration (HI) by enabling the mix-n-matching of integrated circuits (typically known good die) in the same package to deliver higher performance. However, HI also includes the concept of assembling elements beyond integrated circuits, such as optical elements or various sensors including micro-electromechanical systems (MEMS), in devices and products.
The largest challenges discussed to date have been focused on the integrated circuits. This workshop will explore the challenge associated with everything other than the chips which are pulled together to make today’s leading-edge heterogeneous integrations a reality.
Confirmed Speakers Include
Tuesday April 4, 2023
Inter & Intra Package Interconnect
and Assembly - Part 1
The Challenges of Scaling Beyond Moore’s Law and Into the World of 3DHI
While Moore’s Law still provides huge performance, power, and area (PPA) advantages to
some, most semiconductor companies no longer see it as the best technological and economic path
forward for their next-generation designs. There are several trends that have contributed to the
slowing/ending of Moore’s Law including the physical size limitations of a single monolithic die (reticle
limit), low yield tied to large die sizes, and to many, the overall cost of designing at the most advanced
nodes (hundreds of millions of dollars). Instead, the future holds 3D heterogeneous architectures—the
world of More-than-Moore and a new wave of expansion to embrace multi-chiplet 3D packaging to
accommodate the changing landscape of microelectronics.
However, moving to 3D heterogeneous integration (3DHI) comes with many challenges. These
challenges span the 3DHI ecosystem and have a huge impact on the EDA tools/flows required to develop
state-of-the-art 3DHI designs. This presentation will talk about the industry trends and outline many of
the design challenges when engineering teams pivot from monolithic die to 3DHI.
John Park is Product Management Group Director for Advanced Semiconductor Packaging at EDA industry leader Cadence Design Systems, where he leads a team responsible for defining cross-domain solutions and methodologies for IC, package, and PCB co-design and analysis. He is especially focused on developing tools and flows for chiplet-based 3D designs. He has over 40 years of experience in the EDA field and is regarded as an international expert on chiplets, packaging, and heterogenous integration. John has given many conference presentations, done webinars and speeches, and written several articles.
Signal Integrity Analysis at the Dawn of the Interposer Era
The development of applications like high-performance computing (HPC), bespoke Artificial Intelligence (AI) processors, along with advancements in Central Processing Unit (CPU) and Graphical Processing Unit (GPU) chips often involves the use of 2.5D/3D IC technology which necessitate advanced packaging approaches. Achieving the aggressive and desired performance goals can radically alter traditional design methodologies and flows. Designers of high-speed components are now expected to co-simulate die, interposer and package, even printed circuit boards (PCB), to validate designs and sign-off for the signal integrity (SI) of their products with high confidence.
Signal Integrity is standard in analyzing ICs or PCBs, but in the case of silicon interposers a new set of challenges emerge. The combination of silicon density and very high speeds, novel large-scale physics such as through-silicon vias (TSVs) and interposer capacitors, and high-speed signaling over multiple millimeters – orders of magnitude longer than on-chip interconnects, push traditional solutions to their boundaries.
Team dynamics are also a big challenge during design and signoff. Different groups have traditionally collaborated only late in the development cycle. But designing the silicon first and throwing it “over the wall” to package and board designers will not result in design convergence on an optimal, cost-effective solution.
This presentation will explore Ansys multiphysics, advanced workflows and powerful electromagnetic solvers uncovering and helping address SI issues for the most complex silicon interposer architecture, and address the challenges with advanced packaging architectures, thus increasing the confidence of the signoff process and the success of new 2.5D/3D-ICs products.
Dr. Matthew Commens, Senior Manager, Electronics Product Management, at Ansys, Inc., first joined Ansys in 2001 working for Ansoft as an application engineer specializing in high frequency electromagnetic simulation. He is responsible for the strategic product direction of Ansys HFSS and is a recognized expert in the application of computational electromagnetics. Prior to Joining Ansys he worked as an antenna designer and simulation manager at Rangestar Wireless in Aptos, CA and as a nuclear magnetic resonance (NMR) probe designer at Varian Inc. in Palo Alto, CA. He is co-author on five patents in the areas of NMR, antenna design and electromagnetic simulation and holds a Ph.D. in Physics from Washington University in St. Louis, MO. and a B.S. in Physics from University of Missouri-Rolla (now Missouri University of Science and Technology).
Kelly Damalou is Product Manager for the Ansys Semiconductor on-chip electromagnetic simulation portfolio. For the past 20 years she has worked closely with leading semiconductor companies, helping them address their electromagnetic challenges. She joined Ansys in 2019 through the acquisition of Helic, where, since 2004 she held several positions both in Product Development and Field Operations. Kelly holds a diploma in Electrical Engineering from the University of Patras, Greece, and an MBA from the University of Piraeus, Greece.
Assembly Solutions for Cost Effective Heterogeneous Integration with Disparate Die Types
The semiconductor industry is driving to enable high volume integration of disparate die types via Heterogeneous Integration. These die can come from a range of wafer sizes fabricated in different technology nodes. This emerging package type creates new challenges regarding assembly efficiency and yield. Traditionally, flip-chip assembly process flows have utilized a single placement tool for the placement of the single die type onto the target substrate. For applications with multiple die types, a series of placement tools have been configured in a production line, with each tool dedicated to the placement of a specific die type. This paper and presentation explore the implications of this type of solution in the era of Heterogeneous Integration. Impacts on product yield, throughput, manufacturing efficiency, and overall cost of assembly will be explored for a broad range of Heterogeneous Integration die configurations. Based on a sensitivity analysis for the range of die types expected in these applications, a novel approach to optimization of overall assembly economics will be proposed. Appropriateness of this novel approach will be explored for a range of packaging solutions, including Flip-Chip, 2.5D, 3D, and Fan-Out.
Glenn Farris is Vice President of Strategic Marketing for Universal Instruments. In his 30+ year career in the electronics industry, Glenn has transitioned from being a research engineer at NASA to leading marketing organizations for multiple technology companies. Experienced in advanced simulation technology, semiconductor test and measurement, enterprise hardware and software platforms, nanoscale MEMS applications, and dealing with clients in consumer, automotive, medical, and networking industries, he has a broad vision of market trends and a deep understanding of technology challenges.
3D IC Test Strategy
JCET STATS ChipPAC Inc.
3D IC development from true 3D monolithic integration or through diversified advanced packaging technologies that includes 3D WLP, 2.5X/3D interposer/substrate based integration, 3D heterogeneous integration, or Chiplet has emerged as a faster alternative and more feasible strategy than planar transistors scaling as predicted in Moore’s law. OSATs and Foundries have been the major players taking the initiative by offering 3D IC turnkey solutions that include the Test Strategy. However, 3D IC Test Methodologies and DFT solutions have still not been explored much in the global Packaging and Test Research community. Test challenges are obviously still complicated in certain aspects including specific function or parameter testability, defects narrowed down debugging, complex test coverage, and test economics. Determining the appropriate DFT methodology, Boundary Scan Description Language (BSDL) implementation, and how IJTAG complements this 3D IC test strategy for each specific product function and application will be the focus of this concept level discussion.
Uddin Solachuddin is a Senior Expert Engineer, FAE (Field Applications Engineering) at JCET Group with the responsibility of Field Applications Engineering for IC Advanced Packaging and Test, Strategic & Tactical Business Development, New Customer Engagement Process, Technology Development and Promotion, Packaging and Test Roadmap, R&D Engagement and Collaboration, and Strategic Markets Development.
Professional Background: More than 28 years of hands-on and leadership experiences in the OSAT business with various roles in Product Technology Marketing, Sales & Business Development, Product Line Management, Technical Program Management, Test Development, Product/Test Engineering, and Test Manufacturing Operation.
Wednesday April 5, 2023
Silicon Photonics Chiplet Package - Optical Assembly
Ayar Labs, Inc
This presentation provides an overview of the packaging technologies for silicon photonics chiplets, with a focus on the in-package optical components and optical assembly processes. To meet the demands of future high-performance computing, in-package optical I/O chiplets are essential due to their high bandwidth, low energy consumption, low latency, and long reach capabilities. The presentation covers the packaging process flow of TeraPHY™ optical I/O chiplet and describes the electrical and optical architecture of a silicon photonics package module, while acknowledging the need for further development of the optical assembly ecosystem, which is still in its early phase. The presentation also addresses the requirement for 2nd level optical interfaces and the need for a new industry standard. Multiple options for first-level optical interfaces on silicon photonics chips are analyzed and compared. Finally, this presentation assesses the requirements for optical fiber, optical adhesive, and optical assembly equipment for silicon photonics chiplets.
Chong Zhang is a semiconductor packaging expert with over 12 years of experience specializing in advanced packaging and optical assembly. He holds a PhD in mechanical engineering and a master's degree in optics from the University of Central Florida. Currently, he serves as the senior engineering manager at Ayar Labs Inc. where he leads the packaging team to develop packaging solutions for silicon photonics, from prototype to high volume production. Prior to Ayar Labs, Chong worked at Intel ATTD for 8 years, where he focused on substrate pathfinding. Chong has authored over 10 research papers and holds more than 20 US patents and applications.
Enabling high volume data communication – solving the new challenges in PIC wafer testing
JENOPTIK · Advanced Photonic Solutions
Thanks to Photonic Integrated Circuits (PICs), optics is becoming the key to fast data communication. Although not entirely new, PICs are an important future technology. They are already being used to implement applications such as data transceivers, gene sequencing, blood analysis and LiDAR. PICs enable power and bandwidth savings, as well as the creation of micro-photonic devices, novel sensors, and more.
They are produced in a wide variety of designs on wafers using classic lithography methods and with existing equipment from established semiconductor manufacturers. The wafers are manufactured in almost the same way as electronic components. Wafer testing poses its own unique challenge. Due to additional optical components to be tested, the test throughput rates have not yet been achieved as is the case with established IC function tests. Test solutions for optical components still have to be procured and integrated, too. A complex realignment of the optical interfaces of the test device in the submicron range is also required for each chip.
These challenges are solved with Jenoptik´s UFO Probe® card. It now enables simultaneous electrical and optical testing of chips on wafers with only one single probe card. It can be easily integrated into the existing test infrastructure for electrical function testing – thus eliminating the need for expensive investments in stand-alone solutions. The technology of the probe card is designed for high throughputs and for use in high-volume production. It allows chip manufacturers or test houses to get feedback on the performance of each chip at an early stage of production (wafer-level) - for a higher yield.
Tobias Gnausch , Product Manager at Jenoptik, received his diploma in physics from the University of Jena, Germany in 2005 with the specialization on wave-optical design. Following his studies, he worked as a mechanical engineer and developer for interferometric stylus measurement systems at BOSCH.
In 2008, he joined Jenoptik as an optical designer for diffractive optical elements and systems in the field of lithography, laser material processing and ophthalmology equipment. After joining the product management department, he was responsible for the product management of UV micro-optics for semiconductor equipment.
Beginning of 2016, he took over the product development of a new device for PIC wafer-level testing, the UFO Probe® Card. He led this Jenoptik innovation from the early development stage to the final market introduction. With complete product responsibility he ensures the establishment in the market, the continuous product development, and the manufacturing from customer prototypes to series production.
Inter & Intra Package Interconnect
and Assembly - Part 2
Solving Moore’s law Packaging Challenges
The electronics industry is undergoing a major paradigm shift since Moore’s law has been laid to rest with the last published ITRS in 2016. Shifting from CMOS scaling to a packaging focus allows a continuation of Moore’s law and economic growth for decades to come: continuing miniaturization by cramming more functionality onto a smaller and smaller footprint using heterogeneous integration and 3D stacking with a system level focus which Moore too predicted already in his seminal paper from 1965.
Traditional solders no longer fit the ever-increasing performance demands for a cutting- edge interconnect material. Their electrical and thermal conductivity is too low, CTE too high, their proclivity for IMC formation, close coupling of processing with operating temperature, tendency toward creep and potential for wicking and shorts. Many analyses have shown that we need a high-performance copper interconnect material to enable the desired performance increases and to fully utilize new miniaturization technologies such as Cu-pillar/bump and to maximize I/O density to exceed 200,000 in current silicon interposers.
Kuprion Inc. has develop and matured such a material with its ActiveCopperTM system that fulfills many such desired properties and has already been proven to work in numerous spaces. For example, we conducted a system level comparison of ActiveCopper with AuSn solder in LED bonding applications and found a 20-25% performance increase. The presentation will detail the numerous performance and processing advantages of our ActiveCopper on many packaging levels and the enablement of full 3D integration.
Alfred Zinn is founder and CTO of Kuprion Inc., a materials company incorporated in Delaware, 2016. Kuprion is principally engaged in the manufacture and application of engineered copper materials for a wide variety of applications such as surface mount technology, packaging, printed circuit board assembly, printed electronics, 3D printing, injection molding and many thermal applications with special focus on copper-based nanomaterials. The latter are fused to bulk copper taking advantage of the low processing temperatures, and the high electrical and thermal conductivity of bulk copper. Dr. Zinn received multiple SBIR Phase II awards that are currently being executed.
Since the onset of the Covid-19 pandemic in early 2020, Dr. Zinn and the Kuprion team have been investigating ActiveCopper (aCu) as a powerful antimicrobial agent. aCu has been extensively tested against Gram-negative and positive bacteria, non/enveloped viruses including SARS-CoV-2, and multiple resistant strains of bacteria (“superbugs”). In all instances it kills pathogens in as little as 30 sec, which is an unprecedented level of efficacy for copper.
Prior to his current position, Dr. Zinn was a Lockheed Martin Fellow at the Advanced Technology Center (ATC) of the Lockheed Martin Space System Company, in Palo Alto, CA. In this role, Alfred was responsible for the development of nanostructured functional materials (optical, thermal, nano/micro-magnetics), smart materials, high-temperature materials systems, device physics modeling, and high-performance energy conversion devices (solar, high & low-quality heat conversion). His role included identifying profitable adjacencies and licensing opportunities for new technologies and help bring them to market. In addition, he mentored young emerging talent to strengthen the department’s work force and diversity.
Challenges to Develop a Reliable Lead Free Solder Column To Replace Solder Balls in Large Heterogeneous Packages
Martin ("Marty") Hart
Solder balls are well suited for interconnecting normal sized ball-grid array (BGA) components to printed circuit boards (PCB).
However, solder balls may be subject to failure (delamination) caused by excessive stresses inherently found in super-sized Heterogeneous 2.5D packages.
In particular, the growth trend is to make larger and larger BGA processors often exceeding 60mm square in size for hyperscale data centers.
Currently solder column technology is approaching 40 years old and is limited to employing Tin-Lead (SnPb) alloys.
The challenge is to make Lead Free solder columns that satisfy demand for RoHS compliance, while still providing adequate stress relief to enable very large packages and extend the operational life of the system.
We are developing a next generation of solder columns with an exoskeleton copper braided sleeve to make it possible to build fully Lead Free compliant interconnects to replace solder balls for use on large sized Heterogeneous processors.
Our Lead Free non-collapsible Braided Solder Columns reduce the stress between the package and the PCB. Their unique copper sleeve construction also offers lower thermal impedance, as compared to solder balls, possibly reducing the need for a heavy heat sink on top of the chip.
We are extending this technology to support the market trends to scale up the size of chip packaging while maintaining reliability.
In addition to the market and technical requirements, we will be presenting our work to extend the technology along with initial characterization data.
Martin Hart is CEO of TopLine Corporation, graduating with a degree in electrical engineering from California State University in Long Beach. He holds 12 patents in the fields of Column Grid Arrays and Vibration Dampers.
Thursday April 6, 2023
MEMS & Sensors Packaging
Session Overview & Introduction
Roger H. Grace
Roger Grace Associates
Roger H. Grace is president of Roger Grace Associates, a Naples Florida-based marketing consultancy, which he founded in 1982 and which provides market research, strategic marketing communications and business development services to the MEMS, sensors and capital equipment industry. His background includes over 40 years in high frequency analog circuit design engineering, application engineering, project management, product marketing and technology consulting. He was a founding member of MANCEF and currently is its VP of the Americas.
Specializing in microelectromechanical systems (MEMS) and sensors for over 35 years, he is considered a pioneer in this field. He has authored over 40 technical feature articles; organized, chaired, and spoken at over 30 international technical sessions and is frequently quoted as an industry expert in major international technical and business publications.
He is a recipient of the Outstanding Engineering Alumni of the Year in 2004 by Northeastern University and was bestowed the inaugural Sensor Industry Impact Award by Sensors Magazine in 2016. Mr. Grace held the position of visiting lecturer at the University of California at Berkeley from 1990 to 2003. His educational background includes a B.S.E.E. and M.S.E.E. (as a Raytheon Company fellow) from Northeastern University, and the MBA program at Haas Graduate School of Business at U.C. Berkeley.
Packaging of Sensors for High Reliability, Survival and Performance in Extreme Environments
Designing sensor packaging for extreme environments (eg. high temperature, oxidizing, high pressure applications) requires understanding the environment and its underlying physics but also accounting for its effects on the sensor’s packaging material selection, design (i.e. geometry/configuration), its survivability and reliability as well as how the packaging can affect sensor performance. It is especially challenging integrating a MEMS based sensor, i.e. the die, into its packaging with electrical interconnects, ensuring their integrity and survival under these harsh conditions.
In some situations the packaging design may be sufficient for surviving in the environment but may adversely affect sensor performance and reliability over time. This talk will present analysis, some experimental data and “lessons learned” experience regarding the design, fabrication, testing and development of harsh environment sensors and their packaging, particularly for aerospace applications. The focus will be on the unique considerations of designing sensor packaging for these hostile environments, including managing thermal and pressure gradients and minimizing any adverse effects on the encapsulated sensor’s operation, reliability and survivability. To motivate and present our approach the discussion will invoke some unique case studies specific to harsh environment sensor/packaging development. Testing these sensors under relevant conditions also requires specialized test facilities to replicate the extreme aerospace environment. The authors will focus primarily on the hypersonic aero-propulsion environment, as it presents an area of intense interest, in both the civilian and military sectors, in the U.S and to the authors.
Novel Techniques for IC Integration and Packaging Using Additive Technologies
Flexible Hybrid Electronics (FHE) combines a variety of processes coming from industries such as conventional electronics manufacturing, printing, plastics processing, additive manufacturing, laser imaging and robotic assembly. It combines thinned dies, printed components, flexible, conformal materials for electronics enabling new shapes and form factors. NextFlex as a consortium and a manufacturing hub unites a broad community of technology providers, end users and a unique combination of manufacturing tools that together make FHE possible. Additive processes enable us to erase the boundaries between advanced packaging and circuit boards. It also becomes possible to integrate wiring and antennae on and in structures such as aircraft or automotive panels. The combination of processes opens up an exciting level of technology convergence, leading to electronics being integrated at a system level. This talk provides an overview of projects at NextFlex and its members/partners that facilitate US manufacturing innovation for electronics packaging and integration. Among the topics presented will be work on flip chip attachment of thinned bare die microcontrollers on non-traditional substrates and conductors, integration of unpackaged MEMs devices, and use of additive techniques to replace wire bonds for direct IC integration on PCB.
Dr. Beck is a Principal Engineer in the Advanced Technologies Group at NextFlex which integrates smart electronics into new and unique materials to advance Flexible Hybrid Electronics. Her current work demonstrates new fabrication techniques and prototypes in the areas of smart conformable, wearable, and/or physically flexible systems. She received her Ph.D. in Applied Physics from Stanford for research related to MEMS sensors and has previously tackled complex design, device, engineering, and product issues at Hewlett-Packard Labs, HP Divisions, and Bell Laboratories. Her work has included diverse investigations into semiconductor structure, fabrication and characterization, packaging and reliability, materials studies, robotics, solar energy, optoelectronics, high density storage, display technology, and health monitoring. She currently holds 30 US patents, is a Senior Member of IEEE and APS, and is on the board of the IEEE Bay Area MEMS and Sensors Chapter.
Retrospective on MEMS packaging - challenges to be considered / chalenges to be solved (market needs)
The evolution of MEMS packaging will be covered, spanning early pressure sensors in the 1960's that used metal TO cans & custom industrial sensors to plastic automotive packaging starting in the 1980s -1990s with pressure, flow, acceleration sensors and gyroscopes. The talk will then dive into the medical and consumer space, from blood pressure and biocompatible implants to smartphones, gaming and wearable devices. Wafer level packaging and associated MEMS chips scale packaging (CSP) will be summarized with regard to hermetic bonding and CVD sealing technology. Lastly the advent of 3D printing or additive manufacturing and how this is impacting the assembly, prototyping and packaging of sensors made of plastic, glass and metals.
Dr Douglas Sparks is the founder of M2N Technologies LLC. M2N Technologies is a consulting firm specializing in the MEMS and semiconductors technology, product and process commercialization and supply chains. Dr. Sparks has international business experience in these fields in the US, China, Japan and Europe in medical, industrial, aerospace, semiconductors, consumer and automotive applications. He has worked at large MEMS IDMs, start-ups and MEMS foundries. Doug was the CTO of Hanking Electronics which built the first 200mm pure MEMS wafer fab in China. He also led technology acquisition, foundry process and MEMS related product development at Hanking. He founded a microsensor packaging company called NanoGetters, which was acquired by Materion. He was the EVP at Integrated Sensing Systems where he launched multiple microfluidic sensor products, including an FDA approved MEMS drug infusion device and industrial products acquired by Endress + Hauser. Doug worked in automotive sensors and semiconductor fabs with Delphi. Dr. Sparks holds a PhD in materials engineering from Purdue University and has published more than 120 technical papers and has 70 issued patents.
Metal Gel conductor offers increased durability for hard to soft interfaces in Flexible Hybrid Electronics (FHE)
Continuous and real-time monitoring of biopotential and physiological signals is enabled by body-worn electronics, but the adoption of these electronics has been limited because their rigid shape and structure tend to impose restrictions on human body motions and activities. This has led to the development of FHEs as an alternative to conventional on body electronics, bringing together high- performance integrated circuits and flexible, stretchable, and conformable substrates. Establishing a reliable and robust soft-to-hard (substrate-to-IC) interconnection is still a major engineering challenge. With conventional FHE, the mismatch of modulus at the interface amplifies externally applied strains, which lead to frequent failures when the assembly is bent, twisted, or stretched, but with new manufacturing processes and materials developed at Liquid Wire, a far more reliable and robust interconnection mechanism for soft-to-hard transition is now possible. Liquid Wire soft-to-hard interconnections have passed many reliability tests including continuous cyclic strain stretching up to the elastic limits of the substrates, extreme bend-radius testing, as well as hot wash and dry testing in household washing machines. Robust interconnects like this open new pathways for on-body and wearable devices that can move with a user like a textile and have the durability of one as well.
Sai Srinivas Desabathina is a skilled research manufacturing engineer at Liquid Wire Inc, headquartered in Portland, Oregon. He earned his master's degree in manufacturing engineering from Oregon State University and has been an instrumental part of Liquid Wire's team for over three years. Liquid Wire is renowned for producing the world's first washable, stretchable circuits and sensors, and is paving the way for advances in wearable technology. Sai has contributed significantly to the company's success by designing and developing various testing instruments, such as impact test equipment and linear and bi-axial strain systems. His current focus is on investigating and characterizing materials and processes, which have been key to generating reliable and robust stretchable circuits and sensors. Sai is also an active member of Nextflex's Standard and Reliability technical working group.