David Greenlaw is VP of Product Engineering at Nvidia, responsible for the bring-up and production of silicon, boards and systems. Externally, David works with foundry and advanced component suppliers to ensure on-time, high quality products for commercial, automotive and high-performance computing applications.

David has worked on leading edge processors for 25 years, leading many different types of technical teams to success despite barriers related to language, culture, and badge color. He holds master’s degrees in EE from Stanford University and in physics from UT Austin.

Design, Diagnosis, and Digitization for efficient system test and analytics to accelerate time to quality across the End to End Value Chain

The Networking Systems trend continues to push the boundaries on heterogeneous integrations of multiple dies in a package, silicon and photonics convergence, and higher density component integration on the system board. The need to detect known good die under any conditions at the earliest possible test step is key. A die will go through many test steps from its initial wafer test to use in its final application, presenting many opportunities for the known good die to become a known bad die, as electrical, thermal, power, signal integrity and test conditions change from one step to the next.

The use of advanced Si technology nodes brings in lower supply voltages and higher sensitivity to noise, and the use of advanced packaging increases design thermal sensitivity. These trends result in increases in:

• cost to “build in” reliability, voltage and thermal margins;
• higher functional complexity;
• noise/thermal driven interdependence of components on the board,
• more complex failure mechanisms that are harder to partition unless component level DFT and testing is carefully thought out in advance and designed in.

The key to address the challenges above, is to extend high coverage test, characterization and fault isolation methodology that serves the component eco-system to system community and enables tighter component to system co-optimization. The ability of any known bad die to dump out pertinent, actionable, digitized information at any point of fail end to end, that is traceable by a unique identifier, enables a proliferation of data analytics to be done, that can help to drive test coverage earlier in the supply chain, and lead to real-time root cause, quicker corrective action and cost reduction.

In the presentation we will cover differences between component level test and system level test and various paths to cover the gap. We will also show how test data is integrated to partition the failure and to feed into process control of direct suppliers and deeper into supply chain.

The term Known Good Die (KGD) has taken on many new meanings recently for different people and different products. For example, for some it means,” Known Sellable Die”, or “Known Matched Die” or “Known Reparable Die” or even “Not Known Bad Die”. Somehow, we as an industry need to move away from the old way of thinking that a probably good device was good enough to pass on to the next manufacturing or test insertion point. Achieving this will likely take on some big new challenges and opportunities. Ignoring this will make for some very difficult yield challenges as we move forward.

After describing the problem in some detail, this presentation will explore necessary changes we need to consider as the products we ship change from boards to multi-die assemblies and from packaged devices to naked known-good-die.

In his capacity as Director of Business Development, Dave Armstrong works directly with customers and Advantest’s global R&D teams to define develop and deliver creative solutions to the most demanding test challenges. Additionally, Dave is currently the Chairman of the Test focused working group of the Heterogeneous Integration Roadmap.

Prior to joining Advantest in 2004, Dave spent over two decades in HP/Agilent’s IC test group achieving the role of Principal Engineer. Prior to joining HP Dave worked in the semiconductor industry in areas of IC and system design, product/yield engineering, as well as test engineering. Dave Armstrong received degrees in Electrical, Computer, and Environmental Engineering from the University of Michigan in 1974.

Advanced packaging is the obvious path forward to continue the Moore’s Law-like gains that have driven electronics for the last 50 years. To fully realize the benefits of advanced packaging we must drive down interconnect lengths, as they are a primary source of both power consumption and intrinsic delay. Short interconnects lead to tight, intimate assembly. Such assembly is seldom reworkable, and must therefore employ KGD (known good die). The difficulty is that dies are not easy to validate. It is hard even to quantify the definition of “known good.” Can devices be tested at full speed? Can we probe effectively when 10,000s of I/Os are present? In addition, the assembly process itself adds new stresses that can cause latent failures. This talk will discuss repair and redundancy methodologies that overcome yield loss and mitigate the limitations of KGD.

Bob is the president of NHanced Semiconductors, Inc. and has spearheaded the development and delivery of cutting-edge 3D and 2.5D integration technology for high energy physics, medicine, automotive, military, HPC, and other fields. He has managed hardware engineering teams in several organizations, including successful startups. Bob received the 2009 SEMI Award for North America for his pioneering work in 3D IC integration and the 2015 3DIncites Individual Achievement Award.

The industry has moved from hybrid circuits to multichip modules (MCMs), system-in-package (SiP), and heterogeneous integration to chiplets. The names may have changed but the issues remain the same. We have redundancy, built-in self-test (BIST), and new ways to test using artificial intelligence (AI). Despite our name changes and developments in the industry, the availability of known good die (KGD) is still important. This presentation examines the latest package developments, including 3D configurations and chiplets, and strategies to deal with KGD.

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, SMTA, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018. She is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

Gerald Steinwasser is the General Manager of Mühlbauer, Inc., a subsidiary of German Mühlbauer GmbH Co. KG. Gerald has been with the company for more than twenty years and has been focusing mainly on the bare die applications related to RFID-production, high-speed flip chip die sorting and reel-to-reel multi-component application.

Prior to Mühlbauer, Gerald has been already working in the US for a medical company, Gambro Healthcare, where he was responsible for the 24/7 production of a highly automated injection molding department. Originally from Germany, Gerald came to the US the first time in 1988 through an exchange program with the German military. Gerald graduated from the University of the German Armed Forces in Munich with a degree in aircraft & aerospace technology.

Semiconductor manufacturers are continuously driving efforts to put more computing power and speed into less volume. At the same time, consumers are demanding devices with more functionality that integrate a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required.

The demand for higher performance electronics in smaller packages has led to the development of wafer level packaging (WLP), panel level packaging (PLP) and fan-out level packaging. The need for low cost, smaller packages with high density interconnects for cell phones and wearable devices has been leading the development of advanced packaging. All of these advanced packaging techniques involve stacking multiple chips in vertical directions. In DRAM memory packaging, there are as many as eight dies integrated vertically and the manufacturers are trying to keep the thickness of the die as minimal as possible to keep an overall thin package profile.

Backside thinning of fully processed wafers has become a widely used technique in the industry. Typical final wafer thickness in the early 1990s was around 450µm but current wafers are usually thinner than 50µm. As the final wafer thickness is getting thinner, they are becoming more fragile and susceptible to cracks and chips. Chipping and cracks can cause near-term yield and long-term reliability problems. If a chip or crack is discovered during the final processes of advanced packaging, the overall final yield will be lower. If it is not discovered, the end device may not be reliable in the real world and fail for the consumer, a more costly consequence.

As wafers became thinner, the industry started seeing sidewall cracks, inner cracks and micro cracks starting from the kerf or street area initiated from wafer sawing. These types of cracks can cause air bubbles around the cracks during the molding process in fan-out packaging and eventually lead to mold cracking which can lead to lower yields. It would be very beneficial if these types of cracks are detected early and the affected die removed. However, these types of cracks are happening underneath the die surface and are difficult to see with traditional bright field and dark field illuminations because they are underneath the top surface.

Consumer tolerance for device failure is at an all-time low, as they demand more functionality and more convenience from their electronic devices.

Wafer level packaging (WLP), panel level packaging (PLP) and fan-out level packaging advanced packaging techniques all involve extensive use of bumps and die thinning to establish electrical connections in vertical directions. Packaging these vertically integrated die requires the need to provide interlayer connections that are as small and reliable as the multilayer interconnect technologies used within the chip.

This need for vertical connections has created a whole new class of technologies – advanced packaging – with a whole new lexicon of terms and acronyms: through-silicon vias (TSVs), redistribution layers (RDLs), bumps, pillars, nails, under bump metallization (UBM), wafer-level packaging (WLP), fan-in, fan-out, and many more. All of these technologies serve the purpose of providing reliable, electrically isolated, vertical connections, and most, at some point, involve the creation of a conductive “bump” protruding through an insulating layer to carry the signal to the next layer above or below.

As more chips are integrated vertically, overall package thickness increased as well and the common ways to reduce the overall package thickness are by thinning chips or die and reducing bump sizes. As die or chips are getting thinner, they become more fragile and susceptible to cracks or chippings. Cracks or chips can reduce the final package yields or cause long term reliability issues in the consumer devices.

This paper describes inspection challenges for cracks underneath the die surface and possible solutions to overcome the challenges.