Supply chain provenance and traceability of IC components and their test data across the value chain isbecoming increasingly important for the quality, reliability and security of connected electronic devices.It can help reduce costs for tracking and fixing field issues, minimize liability risks and enable IoT device manufacturers to become connected suppliers and offer higher value IoT solutions and services. End-to-end traceability in the value chain, requires collaboration among IC suppliers, foundries, OSATs, contractmanufacturers, device makers and system OEMs serving a variety of application markets. Supply chainprovenance and traceability starts during IC design and manufacturing through an infrastructure that links physical and digital assets with Root of Trust (RoT) based secure chip-to-cloud data exchange.

During IC design a RoT based DFT infrastructure plus sensors are inserted into the circuit. During manufacturing test, an automated process called Zero Touch Chip Enrollment at 1 st power-up (probe test or final test) activates the DFT infrastructure to create a unique Chip ID and a secure communication between the chip and the cloud via middleware utilizing the chip (e.g. ATE, PCB, device, or system). This infrastructure coupled with unique process identifiers enables a secure digital thread on components and data extracted during probe test, final test, PCB test, system test and self-test during field use. The data can be fed to ML/AI analytics engines and used to prevent field failures, enable IoT services from the “chip inside” and evolve digital twins for continuous improvements in quality, reliability and security.

Tom Katsioulas has many years of experience in EDA, semiconductors, electronics, embedded systems, software and IoT applications. Tom is the Board Chair of the GSA Trusted IoT Ecosystem Security. GSA TIES is a collaborative group of companies in the IoT value chain aiming to accelerate industry adoption and monetization of secure and trusted IoT solutions and services for consumer, industrial, automotive, aerospace-defense and the smart infrastructure. Prior to GSA, Tom led the TrustChain business at Siemens focusing on end-to-end solutions for trusted supply chain traceability and IoT solutions for the industrial edge. Tom has held various executive, management and engineering positions at Digital Equipment, Cadence, Synopsys, AmmoCore Technology and Forte Design Automation. Tom holds an M.S. in Electrical Engineering & Computer Science from the University of Massachusetts at Amherst, a B.S. in Computer Engineering from University of Bridgeport, Connecticut and a Certificate on IoT Business Implications and Opportunities from the MIT Sloan School of Management.

Known Good Die (KGD) products are facing economic and logistical headwinds. Meeting this next-generation KGD challenge will require better system insights at every stage: test, assembly and in-field, especially with the 2.5/3D heterogeneous integration revolution underway. To achieve this, we need new ways of understanding SoC health through comprehensive and predictive monitoring methods that combine chip telemetry with ML-driven insights. This session will highlight how proteanTecs’ deep data analytics elevates both quality and performance and minimizes these headwinds. Example applications that will be discussed enable shift left decisions, latent defect detection, application stress monitoring, power optimization and characterization optimization - from wafer testing to system testing and multi-chip packages, as well as visibility D2D interfaces with interconnect monitoring at every stage.

Marc Hutner has been innovating in the areas of Design, Test, DFT and Data Analytics for more than 20 years. In October 2021, he joined proteanTecs where he is Sr. Director of Product Marketing enabling an advanced data analytics approach throughout your products life. Previously, he worked at Teradyne for more than 20 years as a silicon and system architect. A recognized thought leader for design and test at conferences, publications, podcasts and industry roadmaps. Marc has a Bachelor of Computer Engineering (B.Eng) from McGill University in Montreal Canada and an Master of Science in Engineering Management (M.Sc.EM) from Tufts University in Boston Ma.

Though the concept of “Known Good Die” is not new, many economic and technical forces are bringing additional focus to the challenging task of assessing whether an individual device or chiplet is suitable for its intended purpose. Process control’s historical role of reducing manufacturing defects is known to help reliability in the aggregate, but was poorly suited to predict the health of any individual die. Recent advances in high-speed inspection, machine learning and novel algorithmic assessment have overcome prior limitations of inline defect screening in high volume manufacturing. This has resulted in a useful method of recognizing outlier die in the defect domain. This in turn, can shape downstream test insertions and refine engineering decisions on the inherent reliability risk of each die, increasing the confidence that a device is “good.” This presentation reviews the method, use-cases and data that indicate the benefit of the technique in practical application.

A 26 year employee of KLA, Jay leads strategic collaborations with partners across the design, manufacturing and test ecosystem seeking novel methods to improve yield, quality and reliability for mission critical devices. An effort that started with automotive parts has since grown to include Known Good Die for mobile, high performance compute and advanced packaging. Jay and his colleagues hold multiple patents in the area of device quality and outlier recognition.