Heterogenous Integration (HI) of multiple semiconductor dies of different designs in a single advance package to increase functionality provides significant challenges to assembly and test today. As the concept of “Chiplets” - integrating an even larger number of die each smaller than a complete ‘standalone’ semiconductor device in a single package– gains traction these challenges will become even harder. Instead of a single digit number of die, assembly and test will need to accommodate tens of Chiplet die in each package.
As part of the MEPTEC Road to Chiplets series, we will discuss the best-known methods (BKM) of Heterogenous Integration Testability. Properly implementing testability features in the design and having a robust test strategy is essential to make Chiplets commercially viable.
Road Chiplets - Heterogeneous Integration Testability on March 15 & 16, 2022
|Tuesday||March 15, 2022||8:00 - 11:00 am PDT|
|Wednesday||March 16, 2022||8:00 - 11:00 am PDT|
Confirmed Speakers Include
Panel: Will successful Chiplet integration only happen with Testing Coopetition?
Zoe Conroy - Moderator
Advantest Phil Nigh
Broadcom Sreejit Chakravarty
Intel George Harris
Amkor Erik Jan Marinissen
imec Al Yanes