Industry adoption of Chiplets has accelerated much faster than anyone has anticipated, surfacing many critical testability gaps. These include harmonization of EDA tools, methods and flows, solidifying DFT and full-chip debug strategies, developing advanced probing techniques, and creating portable Test content and secure supply chain data sharing among many others. Multi-supplier chiplet Test interoperability through standards and agreements will be key to integrated package manufacturability. We present a Test engineer practitioner’s guide to help industry partners navigate this complex but rapidly-growing product integration trend.

Abram received a BS in Microelectronic Engineering from RIT in 1997 and an MS in Electrical and Computer Engineering from the University of Arizona in 1999 focusing on all-optical methods for parallel database processing. Abram started with Intel in the Fall of 1999, joining the Pentium 4 Design Validation team where he was responsible for driving IO- and clocking-related Test method characterization, small hardware design and novel circuit-related Test method strategies. He moved to Test Pathfinding where he drove module, Test method, Software and prototyping development for Intel’s first internally-designed manufacturing test systems to meet high-volume needs. After a brief period leading a diverse pathfinding and development team in 2018, Abram now leads Test architecture definition for Intel’s future chiplet-based products. Abram chairs the IEEE EPS Test technical committee and is on the advisory board for MEPTEC. Abram holds 12 granted patents and has dozens of internal and external peer-reviewed publications to his name. In his spare time, Abram has a passion for landscape, Milky Way and animal photography, and hiking in the beautiful Oregon wilderness.

As die sizes grow, the probability rapidly increases of die being impacted by inherent wafer defect densities, and therefore, are prone to a lower yield. Realizing this phenomenon, integrated circuit (IC) designers split the functionality of the large die into small chiplets or dielets. Further, platform and system integrators have increasingly realized the need to integrate functional blocks that must be fabricated on distinctly different semiconductor processes. Advanced packaging has enabled the path to integrate chiplets and consolidate functional blocks within a single package. This Heterogeneous Integration (HI) presents a powerful design innovation that allows tighter integration and, in some cases, improved power performance at the system level.

Multi-die packages introduce unique testing challenges, where a test engineer needs to have a broad spectrum of expertise. This may include the testing of radio frequency (RF) devices, mixed signal & analog, high-speed digital, narrow and wide interface memories, photonics, sensors, power control & distribution, embedded passives and various interconnect technologies. The breadth of test expertise must be applied to wafer probe, burn-in (BI), final test (FT) and system-level test (SLT).

Electrical, mechanical and thermal constraints of chiplets impact the package assembly technology. These in turn impact the challenges of package-level testing. To add relevance, this presentation will provide a handful of recent Amkor examples.

Through this presentation, attendees will gain an insight into the challenges of testing and test methodologies that allow data collection on present packaging implementations that result in continuous improvement for future designs.

Vineet joined Amkor in Jan. 2019 and currently leads test technology development for 5G RF and high-speed digital production test methodologies. Before joining Amkor, Vineet worked in test development at Microchip Technology. Prior, he spent 19 years at Intel in a variety of test roles, including tester supplier management, test technology development (burn-in, final and system level test) and RF tester architect. Vineet holds a patent on semiconductor device testers and has earned master’s degrees in physics and electrical engineering from Arizona State University.

The semiconductor industry is rapidly moving towards heterogenous integration and die-disaggregation, driven by the need to keep extending Moore’s Law, as transistor sizes approach atomic scales. More and more products are being defined and created with heterogenous integration by using advanced packaging techniques to combine chiplets from different process nodes and technologies. However, this rapid move towards heterogenous integration has put test in the spotlight. This presentation provides an introduction to Economics of test, test complexity and test cost challenges brought about by die-disaggregation. The presentation covers impacts to wafer sort test, test hardware and collaterals and reviews the need for "characterized KGD - known good die" in order to have a successful disaggregation strategy. Addressing these challenges will require a high degree of innovation and collaboration within the test industry.

Sameer Ruiwale is a Principal Engineer at Intel Corporation, Hillsboro, Oregon. He leads manufacturing development and execution for products in Intel’s client portfolio. Sameer’s passions are overall manufacturing strategy, execution, and manufacturing standardization.

The steady march of Moore’s Law has diminished in terms of transistor density, but due to heterogenous integration and advanced packaging, wafer and singulated‐die test (or “probe”) has seen no relief in demands for increased density or improved electrical performance. The once straight-forward challenge of contacting bond pads accurately has been complicated by the introduction of solder microbumps and the questions of how to contact them or whether to even try. Some chip designers get around probing microbumps literally, by placing special test-only pads or bumps amid the array. Another designer might try to contact several bumps with one probe or to use multiple probe types within one probe card. These and other design decisions are not purely technical but also financial. Every packaged product requires different considerations, but the optimal use of Probe Test is nearly always a compromise of what is possible and what makes sense cost-wise.

Will Thompson is a Sr. Test Engineer in FormFactor’s Characterization Lab. He joined FormFactor after completing his MSME at Stanford University after obtaining his BSME at Temple University in Philadelphia. Prior to becoming an engineer he earned a separate Bachelor’s degree, majoring in both Business Management and Economics.

We have used JTAG for the setup and control of ATE and SLT device testing for many decades. As part of this evolution, I will look at boundary scan, various low speed serial protocols to iJTAG and beyond. Then we review the development and deployment of HSIO protocol-based communication and testing used with new software based functional test models. These high data rate links can stream test containers with different workloads or scan content over multiple USB or PCIe link data rates from ATE to our DUT’s.

Bob Bartlett has a background in electronic warfare, computer science and device physics, Bob has been involved in all aspects of ATE and SLT testing of semiconductor mm-Wave, HSIO, NPU/CPU and complex SOC devices. He has worked in engineering and application roles at various ATE and semiconductor companies and is currently a Principal Engineer at Advantest Corporation focused on next generation test platform deployment for high power, high speed HPC/AI devices.