Scalable Chiplet Interface Testing – Where We are and What We Need As multi-chip-package products gain momentum in the industry we need to carefully consider how we will manage the physical and business aspect of the interfaces. Ensuring quality integrated products for our mutual customers and a constructive partnership among the vendors in the ecosystem starts with the interfaces. This presentation will look at the challenges we have to achieve true modularity while advancing the state of the art – how do we fulfil the vision of achieving the lofty goal that a popular children’s block has achieved in terms of rapid permutation of chiplet combinations? We will take a quick look at the challenges we are seeing supply partnerships, manufacturing and security content collaboration and debug isolation. My goal is to plant some seeds with the audience so that we can begin to identify and plan for out heterogeneous chiplet ecosystem.

Adam is a product development engineer with nearly 30 years of experience in all facets of programmable logic product development. He has worked on all varieties of programmable logic devices—CPLDs, FPGAs, structured ASICs, and tiles. His current responsibility is DFT, test architecture, and manufacturing strategies for Intel’s emerging programmable logic families.

More than Moore’s law, 3D-IC is going to be the new scaling technology adopted by the industry. For testing, 2.5D, in which multiple ICs are packaged side-by-side on a common interposer,has a relaxer test accessibility requirement than that of 3D; and 3D, with dies stacked on top of each other, presents unique challenges for IC test: first, you need to test the die at the wafer, next, stack the good dies together into a package, then manage to test all dies in the stack including the die to die connections, all through the base die. Only partial solutions are available in the industry and there are good progress in enabling the ecosystem. This paper discusses the challenges, new advancements in solution and trend for future:

· Different DFT requirements between 2.5D and 3D

· Key challenges in testing 3D ICs, including how to make sure the full coverage tests are consistent between a die test at the wafer and inside the stack; how to efficiently perform die-to-die test inside the stack with limited DFT accessibility at the base die

· Technologies available providing a solid foundation for 3D IC, including hierarchical DFT to retarget patterns created at the sub-die or die level to the package and IJTAG network to manage and automate all the DFT operations in the stack

· New methodologies entering the industry, for example the standardized die DFT infrastructure to integrate dies in the package through mandatory serial port support utilizing enhanced TAPs and flexible parallel port support using streaming scan network (SSN)

· How the DFT solutions comply with standards such as IEEE1838 defining standardized DFT infrastructure and protocol between dies and IEEE 1687 specifying IJTAG network and a langrage to access, control and operate 3D IC test.

Wu Yang is the Technical & Foundry Programs Manager at Siemens EDA. With more than 20 years of experiences in DFT, silicon learning and testing, Mr. Yang has been a frequent speaker at many conferences and a regular contributor to papers and articles. He delivered multiple tutorials at ITC, ATS, ETS and VTS. Mr. Yang received a MS degree in electrical engineering from Portland State University.

The maturity of Design-for-Test (DFT) technology, in general, comes into better focus when your multi-die package has chips, or chiplets, of all kinds scattered around the substrate: memories, digital cores, communications ports, etc. All require different test, diagnostic, and repair solutions, but all these solutions are well in hand – and most are mature. The difference, today, is that they are applied not to a 2D physical space, but to a virtual 3D physical layout. This presentation will start at the lower-levels of implementation and move up the hierarchy showing how current DFT, diagnostic, and repair technologies as well as standards can be applied to a chiplet-based, multi-die package to enable manufacturing and field scenarios. It will show how DFT structures such as scan and compression can be hooked together with 3rd-party IP DFT, memory BIST, logic BIST, and die-to-die connectivity testing structures, and accessed using standards such as IEEE 1838, 1500, and 1687; and then be further connected to a functional high-speed interface, if required.

Adam Cron is a Distinguished Architect at Synopsys working with customers worldwide on complex DFT, ATPG, and Security issues for digital ICs. He is part of the Hardware Analytics and Test R&D group, and has been with Synopsys for over 24 years. A Syracuse University graduate, Adam also worked in test-related fields at Motorola and Texas Instruments for over 37 years in the industry. Adam is Chair of IEEE Std 1838 which standardized 3D-IC test access, and editor of IEEE Std P1149.4. He is a member of, or has worked with, various IEEE standards’ efforts including 1149.1, 1500, 1687, etc. Adam has also chaired the Test Technology Technical Council's Test Technology Standards Committee which oversees the development of Test standards, and is an IEEE Golden Core recipient. He has authored various papers and book chapters through the years, and is frequently a moderator, panelist, or invited speaker at various test- or security-focused conferences.

Heterogeneous integrated circuits require architecture and design across technical boundaries. Heterogeneity is present in design tools, methodologies, testing schemes, and even business models. In this talk, we will focus on the test aspects of heterogeneous IC design. Architecting systems with chiplets require solving complex testability problems arising from the assembly of dissimilar components and associated cost concerns that can be managed with proper design. The right amount of testing in the final product needs to focus on validating the added manufacturing steps as opposed to over-testing. This talk will go into dissecting test considerations in a system-level design highlighting important test differences when compared with conventional IC testing and PCB level system testing. We will build on the design concepts for system-level testing and cover designers' view of the quality and reliability testing as well.

Jawad is a chip designer with expertise in chiplets, microprocessors, HW/SW co-design, and SerDes. Previously Jawad was the co-founder and CTO of zGlue, Inc., a Silicon Valley chiplet startup that set the direction of chiplet technology and developed a number of heterogeneous integrated circuits. Jawad is now working on his next adventure, Palo Alto Electron. Jawad has been very active with the ODSA workgroup within OCP to help catalyze chiplet ecosystems. Before zGlue, Jawad has held leadership positions at Intel, Samsung, Sun Microsystems, and Transmeta. Jawad holds a Ph.D. degree in Electrical Engineering from Stanford University.

The discussion will start with reviewing the current state and future evolution of 2.5D and 3D wide logic on logic interconnects. Defect trends in such interconnects are reviewed. Test, interconnect-repair, and diagnosis solutions required for such defects are discussed. The discussion ends with the need for a test and repair standard for such Interconnects.

Sreejit Chakravarty is currently a Principal Engineer at Intel Corporation. His current responsibilities include die-disaggregation and interconnect testing, silent data error and functional safety. He is a recognized leader in design for test, silicon reliability and quality. He has published 1 book, authored 130+ IEEE papers, has 20+ issued patents, graduated several doctoral students, served in various capacity at numerous IEEE conferences, and delivered multiple keynote addresses. For his professional work he has been recognized as an IEEE Fellow.

Heterogenous integration (multichip packages) have significant impact on production test, both at wafer level and at final test.  Debug and fault isolation is a key aspect when come to test. Heterogenous integration has created multiple challenges in physical debug, fault isolation and dealing with field returns.  Physical debug is limited with such integration, and needs a good DFT that allows debugging at package level. Wafer level test (for each chiplet)  vs.  package level test have many differences, especially on bring up sequence hence test re-use from wafer to package level is not likely, introducing more variables to debug. It is important to consider interoperability requirement of testing from perspective of product bring up and debug of customer returns.

A known good die (KGD) does not means all shipped bare die will pass at package and system.  The final package integration will need to deliver high quality and high yield packaged products.  How do we effectively debug and isolation failures at final package test?  Test program flow for a 2.5D/3D packaging needs to comprehend inline fault detection and isolation. How do we deal with field return?  To debug a product with a failing system level test , it is important to be to reproduce the failure on ATE and root cause  the failing chiplets. 

Do we need a put together some debug standards for heterogenous integration? IEEE 1838 does not address complete test functionality that enables debug and bring up. How should industry evolve to support debug requirements as we get chiplet from different vendors?   What is needed in each chiplet to provide effective debug and fault isolation at final test and at system level test.

Terrence has been with Intel Malaysia for 16 years. Terrence has been a Test Technologist for his entire career.  Terrence is currently a Senior Principal Engineer in Manufacturing and Product Engineering Organization. He is passionate about end to end product development, solving complex test/manufacturing issues and delivering the product in cost competitive  manner.  His  expertise  is on DFT architecture, HVM test flow, Intel Foveros Technology, Test/Debug for Heterogenous Integration and Creating analog/digital test content.  He holds  4 patents related to areas of Foveros Test and Analog IO Test.

Implementation of machine learning algorithms in the semiconductor arena has gained significant momentum in the past years thanks to flexible computing infrastructures, next generation automated test equipment (ATE) hardware, and much needed solutions for advanced technology nodes (defect types, thermal, power, etc.). This talk will share a methodology to adapt existing test strategies and help mitigate the impact of the everlasting challenges in capacity, quality and cost. It is imperative to have these fundamentals under control as the introduction for chiplet based packaging will only exacerbate the challenges.

Sergio MierSergio Mier is currently the Sr. Director of Test Engineering in Qualcomm’s Product and Test group for the Mobile, AI Cloud, Automotive and IoT business units. Sergio has 21 years of experience in silicon test development for both engineering and production solutions across the portfolio of products including MSMs and MDMs. For the past 4 years, Sergio has been driving the effort to implement more Machine Learning based solutions as part of the initiatives to accelerate learnings for quality, cost reduction and time to market in 7nm and below technology nodes. Sergio has a Master’s Degree in Electrical Engineering from the University of Southern California’s Viterbi School of Engineering in Los Angeles, CA.

Semiconductor test, like many industries, is experiencing a data revolution. With unprecedented demand for electronics of ever higher complexity, and in the face of a bend in the curve of Moore’s Law, manufacturers are moving to a chiplet-based paradigm. These products enable us to cram incomprehensible numbers of components into a growing array of products, resulting in the world’s total output of a staggering 1.6x10^21 transistors in 2021 according to VLSI Research. All those components must be tested, and the corresponding amount of test data would meet any reasonable definition of “big data”. Compounding the problem, the sources of data feeding the test process are becoming more diversified, and traditional production electrical data is being augmented with equipment metadata, optical inspection data, on-chip lifecycle management data, and others, limited only by our collective creativity. The challenge is then to collect, cleanse, and integrate all these distinct data sets so that they can be utilized for workflow optimization and automation.

In this presentation, we describe data analytics-related trends that we observe in the industry and across our customer base. We show how these trends are leading to an increasing need for advanced analytics to tackle a wide array of problems such as achieving parts per billion quality levels and test time optimization. We elaborate the challenges that we see such as high- performance real-time decision-making in test operations and IP and data security across a disaggregated supply chain. We give some specific examples of collaborative solutions being developed to address these issues including adaptive test solutions at parametric (e-test) and production test and show how they solve real industry problems and result in significant improvements in product decision-making, test cost, and yield. We conclude with observations about what we see as crucial next steps.

Ken Butler is a Strategic Business Creation Manager at Advantest. He works with customers on analytics capabilities as part of the Advantest Cloud Solutions platform. Prior to that, he worked for 36 years at Texas Instruments in DFT and test generation, semiconductor reliability, analog product and test engineering, and data analytics. Ken has a BS from Oklahoma State University and an MS and PhD from the University of Texas at Austin, all in electrical engineering. He is a Fellow of the IEEE, a Golden Core member of the IEEE Computer Society, and a Senior Member of the ACM.

As dies get larger, they have a higher probability of being impacted by inherent wafer defect densities, and therefore, are prone to a lower yield. Realizing this phenomenon, integrated circuit (IC) designers split the functionality of the large die into small chiplets or dielets. Further, platform and system integrators have increasingly found the need to integrate functional blocks that must be fabricated on distinctly different fabrication processes. Advanced packaging has enabled the path to integrate chiplets within a single package. Heterogeneous Integration (HI) is a powerful design innovation that allows tighter integration and, in some cases, improved power performance at the system level.

Multi-die packages introduce unique testing challenges, where a test engineer needs to have a broad spectrum of expertise, covering the testing of: radio frequency (RF) devices, mixed signal & analog, high-speed digital, narrow and wide interface memories, photonics, sensors, power control & distribution, embedded passives and various interconnect technologies. This expertise must be applied to wafer probe, burn-in (BI), final test (FT) and system-level test (SLT).

Chiplet’s electrical, mechanical and thermal constraints impact the package assembly technology. These in turn impact the challenges of package-level testing. To add relevance, this presentation will provide a handful of recent Amkor examples.

Through this talk, the attendees will gain an insight into the challenges of testing and test methodologies that allow data collection on present packaging implementations that result in continuous improvement for future designs.

George joined Amkor in 2020 and is currently responsible for Global Test Services operations. Prior to joining Amkor, George led teams and factories for II-VI Inc on VECSEL GaAs products for 3D imaging and preceding that spent 30 years at Texas Instruments engaged in work on memory, analog and SOC products. He holds six US and EU patents on circuit design, wafer fab processing, test and manufacturing controls. George earned masters and bachelor’s degrees in electrical engineering from Syracuse University.

Seeing your MCM packaged chips fail late in the manufacturing process during Final Test is never a welcoming sight especially due to the lost opportunity of selling these chips but also due to the inability to recoup the high costs associated with the testing and packaging that went into the manufacturing of these failed MCM packaged chips. Using data analytics throughout the various manufacturing test stages can possibly help find the source of the problem earlier in the manufacturing cycle. This paper introduces specific analytical methods such as data feed backward and data feed forward that enables test engineers to perform fast root cause analysis and find the source of where the issue originated. Test engineers can then further incorporate preventative measures to bin out suspected die earlier in the process preventing costly failures downstream. Come listen to a real-world customer example of how one customer used these methods together with a cloud-based data analytics solution to reduce their overall test and manufacturing costs.

Guy Cortez is a Staff Product Marketing Manager at Synopsys. His marketing career spans over 20 years where he has held various marketing positions including technical, product/solution, channel/field, integrated/corporate, alliance and business development for companies such as Synopsys, Cadence, VMware and Optimal+. Prior to that, Mr. Cortez spent 12 years as a test engineer at Hughes Aircraft Company (now Boeing), and later at Sunrise Test Systems (which became Viewlogic and later Synopsys). At Hughes, Mr. Cortez was responsible for generating all of the manufacturing test programs for the ASICs developed in the Missile Systems Group division. At Sunrise, Mr. Cortez was a pre- and post-sales Applications Engineer, and also doubled as the company’s instructor.

The industry is faced with finding ways to continue scaling semiconductor devices beyond just process node scaling, and one of the most promising advancements is heterogenous packaging using 2.5D and 3D die stacking inside a package. Using heterogenous packaging, customers can break the barriers of reticle size, enable complex integrations of functions implemented on different silicon manufacturing technologies and bring products faster to the market.

High bandwidth, short range interconnect is a crucial technology to enable these complex integrations, however with the benefits come challenges. The many thousands of interconnect lanes must all perform to spec throughout the entire product lifetime. Traditional test methods based on pass/fail BIST mechanisms fall short of providing the required level of performance and signal integrity information. External measurement equipment is also ineffective once the dies are assembled on the substrate or interposer,­ and all these are irrelevant when the product is deployed and operating in mission mode.

This presentation will focus on the benefits of performance and in-mission health monitoring of 1000s of die-to-die I/Os based on Universal Chip Telemetry (UCT), which consists of monitoring IPs embedded inside the PHY, and a deep data analytics platform. The paper is based on collaborative work with Global Unichip (GUC) on their novel HBM2e and Glink PHY IPs, and the results were demonstrated through multiple test chips.

Nir Sever has over 30 years of technological and managerial experience in advanced VLSI engineering. Before joining proteanTecs, Nir served for 10 years as the COO of Tehuti Networks, a pioneer in high-speed networking Semiconductors. Prior to that, he served for 9 years as Senior Director of VLSI Design and Technologies for Zoran Corporation. Nir was responsible for driving Zoran’s silicon technologies and delivering more than 10 new silicon products each year. Prior to that, Nir held various managerial and technological VLSI roles at 3dfx Interactive, GigaPixel Corporation, Cadence Design Systems, ASP Solutions, and Zoran Microelectronics.

As the semiconductor industry adopts chiplet-based packaging as a primary means to advance higher performance and lower product cost, one of the key challenges will be to maintain at least the same product quality and reliability relative to monolithic ICs. Unlike the traditional methods of building electronic systems based around PCBs and single die ICs where rework is possible to address functionality or quality issues, a different approach to test operations is required for systems that are comprised of chiplets or other SiP-based devices.

To push chiplets into the mainstream, it will be critical to implement cross-functional data collection and sharing in order to support the advanced testing and traceability necessary to ensure performance, quality, and reliability from PCM to final test burn-in. In this presentation, we will discuss three key integrated components necessary to support these advanced packaging needs: a comprehensive semantic data model that will serve as a “single point of truth” for all product lifecycle data and facilitate end-to-end traceability for every component of a chiplet, a big data analytics solution that enables the automatic detection of manufacturing process anomalies to reduce yield variability in manufacturing and chiplet assembly, and AI/ML solutions that can leverage results from prior test steps to accurately predict the outcome of downstream tests and establish selective test populations that can reduce test cost with zero impact on final product quality or reliability.

Kimon Michaels , Ph.D. is a co-founder of PDF Solutions and has served as Vice President of Products and Solutions since July 2010 and has been a Director since November 1995. During his tenure at PDF, Mr. Michaels contributed to the development of the Integrated Yield Ramp business, DFM solutions, and Characterization Vehicle infrastructure. In addition, Kimon holds multiple patents related to semiconductor device characterization. Dr. Michaels received a B.S. in Electrical Engineering, an M.S. E.C.E. and a Ph.D. E.C.E. from Carnegie Mellon University.

Chiplet technologies exacerbate the challenge of ensuring that the final module, containing multiple chiplets, is of high quality and performing to spec. Subtle interactions between chiplets have the potential to harm the overall functionality and performance of a module and the best way to understand these interactions requires analyzing huge volumes of test data gathered from across the supply chain. So while the desire for shared data is legitimate, chiplet manufacturers also have legitimate concerns sharing this type of data with their customers (or suppliers). In this talk, we propose a trusted central hub to provide quality assurance services across the entire supply chain, leveraging data collection and aggregation solutions that are already broadly deployed in much of the supply chain. The hub will provide flexible support for a broad range of analytics capabilities, and protect data ownership and sovereignty through a federated service model and data obfuscation.

Michael brings over 35 years of experience in software development and is focused on long-term innovation and software strategy at NI. Michael joined NI from OptimalPlus, which was acquired by NI in June 2020. During his 15-year tenure at OptimalPlus, he served in several leadership roles including Chief Software Architect and CTO, designing, architecting and prototyping many of its flagship products as well as providing support for sales and marketing. Michael also has extensive experience in enterprise software working as a software architect and R&D leader at Microsoft, SAP and several start-up companies.

In this session, we will explore how modern data mesh architectures with decentralized domains can be extended to allow cross-region and cross-cloud sharing of raw or curated data, metadata and business logic. We will look at how organizations are using the Snowflake Data Cloud to break down data silos, while implementing governance controls like data masking, row-level security and entitlements built on the cloud-agnostic Snowgrid framework. Establishing data marketplaces, like the Snowflake Data Marketplace, provide venues for customers to discover, publish and monetize data products and services across industry verticals.

Vinay Srihari , as a Snowflake Field CTO in the Global Sales Engineering organization, is responsible for promoting adoption of the Data Cloud and synthesizing customer input to guide product direction.

Over a 25-year career leading engineering and field teams in early stage and established data technology companies, Vinay has remained close to the pulse of the customer. He holds 15 software patents in distributed systems, recovery protocols, fault detection and replication.

Bringing technology and solutions to market that deliver lasting customer value is his passion.