E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, SMTA, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018. She is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

Explosion in data generation, transmission, computation and consumption has made hardware and Silicon “hot” again. This has coincided with another inflection point of slow down in Performance, Power & Area (PPA) gains with decreasing process dimensions. As a result of these two diverging phenomenon, there is an urgent need to look at architectures and implementation strategies to scale up to the market needs of designing HW for the data infrastructure market. In this talk, we will look at why “monolithic” only solutions may not suffice as we look at the diversity of solutions needed. Chiplets are here to stay and we will look at the challenges and opportunities they present. It will require a collaborative approach to solve the challenges across the semiconductor industry.

Executive Vice President, Central Engineering, System-on-Chip Group

Sandeep Bharathi is Marvell’s Executive Vice President of Central Engineering, System-on-Chip Group. In this role, Sandeep oversees the development of SoCs for various end markets in advanced process technologies. He is a recognized expert in digital and mixed-signal design, IP and product development.

Prior to joining Marvell in 2019, Sandeep served as Vice President of Engineering at Intel, where he led FPGA product and technology development. Previously, he held a variety of senior engineering leadership roles at both Xilinx and Advanced Micro Devices.

A longtime industry veteran, Sandeep is a proven innovator and has brought multiple CPUs, GPUs, FPGAs, SoCs and custom designs to market, which together have generated billions of dollars in cumulative revenue. He earned a B.E. in Electronics Engineering from Bangalore University, an M.S. in Electrical Engineering from the New Jersey Institute of Technology, and is also a graduate of the Stanford Executive Program.

Semiconductor innovation is transforming how multi-die system is architected, designed, and manufactured.

As manufacturing technology around advanced packaging evolves, the performance, density, and energy efficiency of multi-die designs being enabled have experienced tremendous advancement in the past decade. The next decade is the time for the manufacturing and EDA industry to give wings to chip designers of the More-than-Moore era of integration and disaggregation. There will be three driving forces for this manufacturing-design joint movement: diversity, velocity and robustness.

Diversity: The development of AI, 5G and further proliferation of IoT everywhere will demand more ways to place the dies and chiplets together.

Velocity: The current chip shortage will likely put more pressure on accurate forecasting, as well as faster design implementation and iteration.

Robustness: Ensuring time-zero manufacturing quality and life-time reliability and safety of chips in trillions of connected things will need proactive inclusion of sensors in the design and corresponding design, debug, and monitoring methodology.

In this talk, we will introduce the market trend, the roles of die-to-die interface IP and end-to-end EDA automation co-optimized with manufacturing technology, and how the chiplet paradigm will enable productivity and quality for More-than-Moore integration and disaggregation.

Ming Zhang is a Distinguished Architect at Synopsys, leading corporate strategy for 3DIC. Prior to Synopsys, he has been a circuit designer at Intel specializing in low-power and fault-tolerant designs, foundry engineer at Samsung specializing in DFX, software developer at AI startups working on algorithm development and cloud deployment, and most recently the co-founder & CEO of a chiplet startup – zGlue.

Dr. Zhang holds a Ph.D. EE in VLSI from the University of Illinois at Urbana-Champaign (UIUC), M.S. in MEMS from UIUC, and a B.S. in Physics from Peking University in China.

Heterogenous integration (multichip packages) will have a significant impact on production testing -- both at the wafer probe level and at Final Test. More test content must be driven back to wafer probe test to enable reasonable Final Test yield. But at the same time, it is becoming impractical to probe the required signal IO pins at wafer probe. As the use of chiplets emerge, there are some design-for-test standards being proposed -- but these proposals do not cover all types of chiplets.

The final package integrator will need to pull all these dies and chiplets together -- and deliver high quality packaged products. But will these integrators have to repeat die-level tests at the final package test ? Will the test information be available from each of the chiplet providers? Also, will the integrator have to enable die-level traceability of each component ? Why will full End-to-End data analytics be critical? How should the industry evolve to support these requirements?

As conventional technology scaling becomes harder, 2.5D integration provides a viable pathway to building larger systems at lower cost. We start with discussing cost/performance tradeoffs in SoC disaggregation and pathfinding 2.5 interconnect technologies, identifying areas where technology development would help design metrics substantially. Next, we discuss our experience designing a 2000 chiplet waferscale processor system, pointing out key challenges and solutions.

Chiplets are the logical outcome of several factors affecting the IC industry’s drive towards higher and higher performance and to accomplish these requirements at a minimum total product cost. For this discussion, a chiplet is considered one of several functional blocks which normally resides inside a system-on-chip (SoC) design. Common chiplets are I/O die and CPU or compute chiplets.

Leading integrated circuit (IC) foundries are already shipping 7 nm and 5 nm process node wafers and will soon be shipping 3 nm. Wafer costs continue to soar as high transistor densities require more expensive processing for fabrication. Even with flat defect densities from node to node the cost per unit area of silicon is increasingly nonlinear. These base-level economics have caused a re-evaluation of the silicon chip design, fabrication and packaging technologies which serve current leading-edge and future high-performance products in the data center, personal computing and edge device segments.

Total product cost includes several important elements. Material costs including silicon and packaging are big drivers, with silicon costs usually dominating. Other important elements of total product cost include time-to-market (TTM) and design costs.

Chiplets allow functional blocks that require industry-leading transistor performance to be derived in the most current or suitable silicon node. A good example of these would be the CPU compute block. Other functional blocks, which do not need a leading-edge silicon node, could use N1 or N2 generation silicon. The results are physically smaller die or chiplets that can be combined and reused as needed to derive one or many different products. In this manner the design resource can design once and several functional blocks can conceptually use the same chiplet.

By using smaller chiplets (smaller than an SoC) wafer yields can be substantially increased and the cost per square millimeter of silicon for the total product can be reduced.

From an IC packaging standpoint, the broad approach of heterogeneous packaging has been the packaging industry’s contribution to this endeavor. The industry initiated this most recent effort for multi-die chiplet-based IC packaging with 2.5D Through Silicon Via (TSV) products. These allow very high-density DRAM (High Bandwidth Memory or HBM) to be implemented alongside the application-specific integrated circuit (ASIC) in the same IC package. In this instance, these dies were not chiplet based, at least initially, but the die-die interface density, very fine-pitch CuP bumping, and assembly methods were very similar to those needed by chiplet-based products.

To further refine our capabilities to address the chiplet-based heterogeneous package approach, Amkor has developed several key packaging technologies to permit several chiplets to be integrated into one product package.

Additionally, these chiplet blocks may also be integrated with dedicated ASICs and memory into one IC package. These end products include high-density multi-die offerings which use a conventional IC package substrate and Flip Chip BGA (FCBGAs) packages, as well as very fine-line constructions such as 2.5D TSV and High-Density Fan-Out (HDFO) offerings. New chiplet integrations using advanced HDFO (S-SWIFT™) are now being qualified to permit fine line routing down to 2 µm line and 2 µm space with 6-layer construction. This module fabrication technology has been developed over the last 3 years and upgraded to realistically permit the integration of chiplets and HBM designs.

The future of these packaging technologies is bright. New product designs in this packaging class have increased 4-fold over the previous year. The silicon architectural flexibility, IP reuse, time-to-market and lower overall cost continue to drive this innovation in the industry as Amkor delivers advances in heterogeneous IC packaging to meet the needs of a diverse set of chiplet-based designs.

S-SWIFT™ is a trademark of Amkor Technology, Inc. All trademarks are the property of their respective owners.

© 2021, Amkor Technology, Inc. All rights reserved.

David joined Amkor in 1997 and has held various management positions in quality, substrate technology and advanced interconnect and wafer level package development. He has worked in the assembly and packaging industry for more than 30 years, also holding positions in product and package development at Surfect Technologies and RF Micro Devices. David has been issued 22 patents in semiconductor packaging. He holds a BS degree in chemical engineering from Arizona State University and an MBA from University of Phoenix.

William Chen (Bill) holds the position of ASE Fellow & Senior Technical Advisor at ASE Group. Prior to joining the ASE, he was Director at the Institute of Materials Research & Engineering (IMRE) in Singapore, following a distinguished career at IBM Corporation. Bill is a past President of the IEEE Electronics Packaging Society. He has been elected a Life Fellow of IEEE and a Fellow of ASME. In 2018, he received the IEEE Electronics Packaging Field Award, recognizing his contribution to electronic packaging, from research & development through industrialization.

Bill chairs the Heterogeneous Integration Roadmap initiative, co-sponsoed by three IEEE Societies (EPS, EDS & Photonics) together with SEMI & ASME EPPD.

This talk will review recent progress in the Open Domain-Specific Architecture - an industry consortium that aims to enable a marketplace of chiplets. The ODSA aims to create both an open physical and logical chiplet interface. The talk will present progress on the interface and progress on prototyping and workflows in the ODSA.

Bapi Vinnakota is a System Architect with Broadcom. After a Ph.D. at Princeton, he taught at the University of Minnesota, where he received an NSF CAREER and IBM Faculty Development Awards. He joined Intel through an acquisition and worked in networking technology. At Netronome, he created and ran open-nfp.org (http://open-nfp.org/), a service for research in networking. He's here representing the Open Domain-Specific Architecture project. The ODSA has active volunteers from over 50 companies and aims to define an open chiplet

Chiplets are being rapidly adopted within Intel and the rest of the industry. However, apart from the multiproduct and multivendor usage demonstrated with HBM and with Intel’s AIB ecosystem, most chiplet usage has been confined to integrating die designed by the same company applied to building chips for the same product types.

In theory, a chiplet approach should be able to reduce portfolio (product and project) costs, scale innovation and delivery capabilities, and improve time to solution. However, it is important to manage the associated trade-offs around tiling overheads, thermal and I/O escape constraints, and associated supply chain and economic considerations.

In practice, the industry must address key adoption and scaling prerequisites to broadly achieve these benefits including volume attach points, fully specified interface standards, enabling building blocks and tools/flows/methods, and broad market production capabilities. Key early adopter use cases to address include layer 1-only connectivity for optical I/O and SerDes attach and XPU and I/O attach using CXL/PCIe (which can also support a uniform software model across different types of integration).

By addressing these prerequisites, the industry can reshape how companies can collaborate to build many types of chips in the future.

Rob Munoz is a Principal Engineer in Intel’s Design and Engineering group located in Austin, TX. His day job is architecture for custom/semicustom/standard products targeted at wireless infrastructure (largely the radio access network portion). He also co-leads the cross-Intel Chiplet Working Group. He has been with Intel since November 2014, joining as part of Intel’s acquisition of LSI/Avago’s networking business. At LSI/Avago/Agere he was previously a Distinguished Engineer focusing on architecture and systems engineering for the Axxia and PayloadPlus multicore/network processor product families. He started his career at Bell Labs in Columbus, OH where he worked on telecommunications signaling systems. He has an MS in Computer Science from UT Austin and currently has 15 granted patents.

Heterogeneous Integration (HI) will launch unprecedented changes, not only in multiscale system complexity, functionality and density (using multiplicity of 2.5D and 3D stacks of chips and chiplets), but also in multi-physics diversity of technologies (involving combinations of digital, analog, power, RF, sensors, MEMS, photonics, chem/bio-electronics, quantum, and other devices) within a unified system-in-package (SiP) configuration. Such extreme complexity will inevitably result in increased densities of intrinsic material defects, manufacturing flaws and stochastic variabilities. HI systems of the future require a convergence of semiconductor and packaging technologies and will have to combine increasingly resilient and fault-tolerant designs with self-monitoring, self-cognizance and varying degrees of adaptive reconfiguration and self-healing capabilities, to provide high reliability and availability. These systems will have cradle-to-grave reliability management using ‘digital twins’ which will be based on hybrid methods that will combine bottom-up reliability physics (RP) approaches with top-down artificial intelligence (AI) methods. In addition, the value chain of product ownership will also alter dramatically, thus raising fundamental questions about the value proposition of reliability assurance activities. The Reliability TWG in the HI roadmap lays out the scope, challenges, disruptive opportunities and potential approaches for assuring that future HI systems will be sufficiently reliable over the next 0-5, 5-10 and 10-15 years.

Abhijit Dasgupta is Jeong H. Kim Professor of Mechanical Engineering at the University of Maryland (UMD), with research experience in the microscale and nanoscale mechanics and reliability physics of engineered materials used in conventional and additively manufactured 3D flexible electronic packaging and intelligent microsystems. He holds a Ph.D. in Theoretical and Applied Mechanics from the University of Illinois at Urbana-Champaign (UIUC), and has been a principal investigator at the Center for Advanced Life Cycle Engineering (CALCE) at UMD for over 30 years, conducting research in reliability physics, design for reliability, accelerated stress testing, and real-time health management. He has published over 300 articles and conference papers; served on editorial boards of three international archival journals; presented over 45 workshops and short courses; helped form research and educational roadmaps for the electronics industry, and provided consulting services to numerous industry leaders. He has presented numerous keynote talks at international conferences, received 6 best-paper awards and received 8 major awards in recognition of his research and educational contributions. He is an ASME Fellow, past Chair of the ASME Electronic and Photonic Packaging Division (EPPD), past member of the ASME Design, Manufacturing and Materials Segment Leadership Team (DMM-SLT) and Current Chair of Reliability Technology Working Group in the Heterogeneous Integration Roadmap (HIR) Team sponsored by IEEE/ASME/SEMI/IEPS/EDS.