Category Archive

June 12-13, 2024

There is a growth in “application specific” devices. So instead of developing the next generation of a general purpose microprocessor or microcontroller, many companies are developing application specific processors which are optimized for the desired compute workload especially for data center deployment. At the same time, heterogeneously integrated devices, such as those built with Chiplets, are increasing in size and the number of different use cases (or use patterns) is growing. For all these reasons of increased complexity, greater size, and shorter time to market it is essential to use artificial intelligence, especially machine learning (ML), in the design, packaging, and test of semiconductor devices.

November 29, 2023

With heterogeneous integration (HI) and advanced packaging becoming the dominant drivers of progress in many electronic products, the need for collaboration and a robust ecosystem has grown. In the earlier days of Moore’s Law when the silicon node was the main metric and driver for advances in the semiconductor industry, the International Technology Roadmap for Semiconductors (ITRS) was the primary vehicle for coordinating these activities.

Now, though, there is no single metric specifying the details and timing for progress enabled by integration technologies, so new approaches are needed. There have been road mapping efforts that have laid much of the groundwork, such as the Heterogeneous Integration Roadmap (HIR), but more work is needed to have such efforts fully embedded in the industry’s path forward. Similarly, there are various interconnect standards emerging, such as UCIe, but with more (and more complicated) integration scenarios, these standards cover only a fraction of what’s needed.

April 4 – 6, 2023 – Online

Today advanced semiconductor packaging is already delivering Heterogeneous Integration (HI) by
enabling the mix-n-matching of integrated circuits (typically known good die) in the same package to
deliver higher performance. However, HI also includes the concept of assembling elements beyond
integrated circuits, such as optical elements or various sensors including micro-electromechanical
systems (MEMS), in devices and products.

The largest challenges discussed to date have been focused on the integrated circuits. This workshop will
explore the challenge associated with everything other than the chips which are pulled together to make
today’s leading-edge heterogeneous integrations a reality.

September 7, 2022 – Online

Today’s advanced packaging requires test engineers and product managers to think beyond the die. KGx (Known Good ____) starts with the architecture and product planning, needs to be supported by the design, and is delivered by the test and assembly operations. This requires new thinking and cross-functional approaches to test in the quest for KGx.

Join us at the KGx Workshop on September 7, 2022 for a cross-functional view of challenges and solutions for achieving KGx starting with wafer quality!

May 10 – 12, 2022 – Online

The semiconductor industry has come a long way from the days where the semiconductor die design / layout team simply passed the device off to another team to “handle” the packaging. Now there are packaging Design Integration (DI) teams who are responsible for “co-designing” the packaging and other processing while the chip is being designed. These teams resolve interdependencies, develop test vehicles, and manage risk to make sure there is a viable product.

As part of the MEPTEC Road to Chiplets series, we will discuss the role and challenges of DI in the upcoming storm of Chiplets. Properly implementing and developing methodologies to manage DI is essential to make Chiplets commercially viable.

March 15 & 16, 2022 – Online

Heterogeneous Integration (HI) of multiple semiconductor dies of different designs in a single advance package to increase functionality provides significant challenges to assembly and test today. As the concept of “Chiplets” – integrating an even larger number of die each smaller than a complete ‘standalone’ semiconductor device in a single package– gains traction these challenges will become even harder.

We will discuss the best-known methods (BKM) of Heterogeneous Integration Testability at Road to Chiplets – Heterogeneous Integration Testability.

November 9 – 11, 2021 – Online

Data sharing and analysis of test results and other production ‘signals’ are critical enabling technologies
to make Chiplet-based advanced packaging practical. To transition Chiplets from design of experiments and prototypes to commercial reality
will require cross-functional data sharing across factories and suppliers. New data sources including new
test steps and new ways of analyzing and sharing data are essential.

We will explore the new types of data and tests required to make products using a Chiplet
approach practical at Road to Chiplets – Data & Test.

July 13-14, 2021 – Online

The concept of “Chiplets” – integrating multiple die smaller than complete “stand alone” semiconductor devices using advanced packaging – has firmly captured the attention of the semiconductor industry. The foundational technologies to enable this advanced packaging have been explored in detailed at industry events. MEPTEC through a series of events will cover the practical aspects of designing, implementing (packaging), and testing Chiplets as this cross-functional knowledge is critical to transitioning such devices from science projects to commercial reality.

Join us as we focus on the high-level decisions that need to be made to implement a product using a Chiplet approach.